283 lines
13 KiB
LLVM
283 lines
13 KiB
LLVM
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; ADDHNB
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define <vscale x 16 x i8> @addhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: addhnb_h:
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; CHECK: addhnb z0.b, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @addhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: addhnb_s:
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; CHECK: addhnb z0.h, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @addhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: addhnb_d:
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; CHECK: addhnb z0.s, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 4 x i32> %out
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}
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; ADDHNT
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define <vscale x 16 x i8> @addhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: addhnt_h:
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; CHECK: addhnt z0.b, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @addhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: addhnt_s:
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; CHECK: addhnt z0.h, z1.s, z2.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @addhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: addhnt_d:
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; CHECK: addhnt z0.s, z1.d, z2.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c)
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ret <vscale x 4 x i32> %out
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}
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; RADDHNB
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define <vscale x 16 x i8> @raddhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: raddhnb_h:
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; CHECK: raddhnb z0.b, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @raddhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: raddhnb_s:
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; CHECK: raddhnb z0.h, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @raddhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: raddhnb_d:
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; CHECK: raddhnb z0.s, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 4 x i32> %out
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}
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; RADDHNT
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define <vscale x 16 x i8> @raddhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: raddhnt_h:
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; CHECK: raddhnt z0.b, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @raddhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: raddhnt_s:
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; CHECK: raddhnt z0.h, z1.s, z2.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @raddhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: raddhnt_d:
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; CHECK: raddhnt z0.s, z1.d, z2.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c)
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ret <vscale x 4 x i32> %out
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}
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; RSUBHNB
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define <vscale x 16 x i8> @rsubhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: rsubhnb_h:
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; CHECK: rsubhnb z0.b, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @rsubhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: rsubhnb_s:
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; CHECK: rsubhnb z0.h, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @rsubhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: rsubhnb_d:
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; CHECK: rsubhnb z0.s, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 4 x i32> %out
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}
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; RSUBHNT
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define <vscale x 16 x i8> @rsubhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: rsubhnt_h:
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; CHECK: rsubhnt z0.b, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @rsubhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: rsubhnt_s:
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; CHECK: rsubhnt z0.h, z1.s, z2.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @rsubhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: rsubhnt_d:
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; CHECK: rsubhnt z0.s, z1.d, z2.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c)
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ret <vscale x 4 x i32> %out
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}
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; SUBHNB
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define <vscale x 16 x i8> @subhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: subhnb_h:
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; CHECK: subhnb z0.b, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @subhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: subhnb_s:
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; CHECK: subhnb z0.h, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @subhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: subhnb_d:
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; CHECK: subhnb z0.s, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 4 x i32> %out
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}
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; SUBHNT
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define <vscale x 16 x i8> @subhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
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; CHECK-LABEL: subhnt_h:
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; CHECK: subhnt z0.b, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @subhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
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; CHECK-LABEL: subhnt_s:
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; CHECK: subhnt z0.h, z1.s, z2.s
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @subhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
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; CHECK-LABEL: subhnt_d:
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; CHECK: subhnt z0.s, z1.d, z2.d
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c)
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ret <vscale x 4 x i32> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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