55 lines
2.0 KiB
LLVM
55 lines
2.0 KiB
LLVM
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
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;
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; Compares
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;
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define i32 @cmpge_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: cmpge_nxv16i8:
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; CHECK: cmpge p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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;
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; Immediate Compares
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;
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define i32 @cmpge_imm_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
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; CHECK-LABEL: cmpge_imm_nxv16i8:
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; CHECK: cmpge p0.b, p0/z, z0.b, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer)
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%2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%3 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)
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%conv = zext i1 %3 to i32
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ret i32 %conv
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}
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;
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; Wide Compares
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;
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define i32 @cmpge_wide_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: cmpge_wide_nxv16i8:
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; CHECK: cmpge p0.b, p0/z, z0.b, z1.d
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
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declare i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
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