77 lines
3.7 KiB
LLVM
77 lines
3.7 KiB
LLVM
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; Masked Loads
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;
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define <vscale x 2 x i64> @masked_zload_nxv2i8(<vscale x 2 x i8>* %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i8:
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; CHECK-NOT: ld1sb
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; CHECK: ld1b { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef)
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%ext = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 2 x i64> @masked_zload_nxv2i16(<vscale x 2 x i16>* %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i16:
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; CHECK-NOT: ld1sh
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; CHECK: ld1h { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i16> undef)
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%ext = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 2 x i64> @masked_zload_nxv2i32(<vscale x 2 x i32>* %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i32:
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; CHECK-NOT: ld1sw
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; CHECK: ld1w { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> undef)
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%ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 4 x i32> @masked_zload_nxv4i8(<vscale x 4 x i8>* %src, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv4i8:
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; CHECK-NOT: ld1sb
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; CHECK: ld1b { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> undef)
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%ext = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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}
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define <vscale x 4 x i32> @masked_zload_nxv4i16(<vscale x 4 x i16>* %src, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv4i16:
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; CHECK-NOT: ld1sh
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; CHECK: ld1h { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> undef)
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%ext = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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}
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define <vscale x 8 x i16> @masked_zload_nxv8i8(<vscale x 8 x i8>* %src, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv8i8:
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; CHECK-NOT: ld1sb
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; CHECK: ld1b { [[IN:z[0-9]+]].h }, [[PG:p[0-9]+]]/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %src, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> undef)
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%ext = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %ext
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}
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declare <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>*, i32, <vscale x 2 x i1>, <vscale x 2 x i8>)
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declare <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>*, i32, <vscale x 2 x i1>, <vscale x 2 x i16>)
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declare <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>*, i32, <vscale x 2 x i1>, <vscale x 2 x i32>)
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declare <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>*, i32, <vscale x 4 x i1>, <vscale x 4 x i8>)
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declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>*, i32, <vscale x 4 x i1>, <vscale x 4 x i16>)
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declare <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>*, i32, <vscale x 8 x i1>, <vscale x 8 x i8>)
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