248 lines
15 KiB
LLVM
248 lines
15 KiB
LLVM
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; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; All these tests create a vector tuple, insert z5 into one of the elements,
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; and finally extracts that element from the wide vector to return it. These
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; checks ensure that z5 is always the value that is returned.
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;
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; Insert into two element tuples
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;
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; tuple: { tuple2.res0, tuple2.res1 }
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; insert z5: { z5 , tuple2.res1 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple2_nxv8i32_elt0:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
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%ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 0)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple2.res0, tuple2.res1 }
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; insert z5: { tuple2.res0, z5 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple2_nxv8i32_elt1:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
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%ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 1)
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ret <vscale x 4 x i32> %ext
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}
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; This test checks the elements _not_ being set aren't changed.
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; tuple: { tuple2.res0, tuple2.res1 }
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; insert z5: { tuple2.res0, z5 }
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; extract z0: ^^
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define <vscale x 4 x i32> @set_tuple2_nxv8i32_elt1_ret_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple2_nxv8i32_elt1_ret_elt0:
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; CHECK-NEXT: ret
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%tuple = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1)
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%ins = call <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %ins, i32 0)
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ret <vscale x 4 x i32> %ext
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}
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; Test extract of tuple passed into function
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define <vscale x 4 x i32> @get_tuple2_nxv8i32_elt1(<vscale x 8 x i32> %tuple) #0 {
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; CHECK-LABEL: get_tuple2_nxv8i32_elt1:
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; CHECK-NEXT: mov z0.d, z1.d
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; CHECK-NEXT: ret
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32> %tuple, i32 1)
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ret <vscale x 4 x i32> %ext
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}
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;
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; Insert into three element tuples
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;
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; tuple: { tuple3.res0, tuple3.res1, tuple3.res2 }
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; insert z5: { z5 , tuple3.res0, tuple3.res2 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple3_nxv12i32_elt0:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
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%ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 0)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple3.res0, tuple3.res1, tuple3.res2 }
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; insert z5: { tuple3.res0, z5 , tuple3.res2 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple3_nxv12i32_elt1:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
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%ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 1)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple3.res0, tuple3.res1, tuple3.res2 }
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; insert z5: { tuple3.res0, tuple3.res1, z5 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple3_nxv12i32_elt2:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
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%ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 2, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 2)
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ret <vscale x 4 x i32> %ext
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}
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; This test checks the elements _not_ being set aren't changed.
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; tuple: { tuple3.res0, tuple3.res1, tuple3.res2 }
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; insert z5: { tuple3.res0, z5 , tuple3.res2 }
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; extract z2: ^^
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define <vscale x 4 x i32> @set_tuple3_nxv12i32_elt1_ret_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple3_nxv12i32_elt1_ret_elt2:
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; CHECK-NEXT: mov z0.d, z2.d
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; CHECK-NEXT: ret
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%tuple = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2)
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%ins = call <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %ins, i32 2)
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ret <vscale x 4 x i32> %ext
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}
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; Test extract of tuple passed into function
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define <vscale x 4 x i32> @get_tuple3_nxv12i32_elt2(<vscale x 4 x i32> %z0, <vscale x 12 x i32> %tuple) #0 {
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; CHECK-LABEL: get_tuple3_nxv12i32_elt2:
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; CHECK-NEXT: mov z0.d, z3.d
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; CHECK-NEXT: ret
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32> %tuple, i32 2)
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ret <vscale x 4 x i32> %ext
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}
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;
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; Insert into four element tuples
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;
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; tuple: { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
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; insert z5: { z5 , tuple4.res1, tuple4.res2, tuple4.res3 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt0(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple4_nxv16i32_elt0:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
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%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 0, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 0)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
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; insert z5: { tuple4.res0, z5 , tuple4.res2, tuple4.res3 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt1(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple4_nxv16i32_elt1:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
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%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 1, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 1)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
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; insert z5: { tuple4.res0, tuple4.res1, z5 , tuple4.res3 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple4_nxv16i32_elt2:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
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%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 2, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 2)
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ret <vscale x 4 x i32> %ext
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}
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; tuple: { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
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; insert z5: { tuple4.res0, tuple4.res1, tuple4.res2, z5 }
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; extract z5: ^^
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define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt3(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple4_nxv16i32_elt3:
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: ret
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%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
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%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 3, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 3)
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ret <vscale x 4 x i32> %ext
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}
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; This test checks the elements _not_ being set aren't changed.
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; tuple: { tuple4.res0, tuple4.res1, tuple4.res2, tuple4.res3 }
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; insert z5: { tuple4.res0, tuple4.res1, tuple4.res2, z5 }
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; extract z2: ^^
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define <vscale x 4 x i32> @set_tuple4_nxv16i32_elt3_ret_elt2(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1,
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<vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3,
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<vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5) #0 {
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; CHECK-LABEL: set_tuple4_nxv16i32_elt3_ret_elt2:
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; CHECK-NEXT: mov z0.d, z2.d
|
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; CHECK-NEXT: ret
|
||
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|
%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3)
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||
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%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %tuple, i32 3, <vscale x 4 x i32> %z5)
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%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 2)
|
||
|
|
ret <vscale x 4 x i32> %ext
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test extract of tuple passed into function
|
||
|
|
define <vscale x 4 x i32> @get_tuple4_nxv16i32_elt3(<vscale x 16 x i32> %tuple) #0 {
|
||
|
|
; CHECK-LABEL: get_tuple4_nxv16i32_elt3:
|
||
|
|
; CHECK-NEXT: mov z0.d, z3.d
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %tuple, i32 3)
|
||
|
|
ret <vscale x 4 x i32> %ext
|
||
|
|
}
|
||
|
|
|
||
|
|
attributes #0 = { nounwind "target-features"="+sve" }
|
||
|
|
|
||
|
|
declare <vscale x 8 x i32> @llvm.aarch64.sve.tuple.create2.nxv8i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 8 x i32> @llvm.aarch64.sve.tuple.set.nxv8i32.nxv4i32(<vscale x 8 x i32>, i32, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv8i32(<vscale x 8 x i32>, i32)
|
||
|
|
|
||
|
|
declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.create3.nxv12i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 12 x i32> @llvm.aarch64.sve.tuple.set.nxv12i32.nxv4i32(<vscale x 12 x i32>, i32, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv12i32(<vscale x 12 x i32>, i32)
|
||
|
|
|
||
|
|
declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32>, i32, <vscale x 4 x i32>)
|
||
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32>, i32)
|