135 lines
5.9 KiB
LLVM
135 lines
5.9 KiB
LLVM
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; RUN: llc -aarch64-sve-vector-bits-min=128 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefix=NO_SVE
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; RUN: llc -aarch64-sve-vector-bits-min=256 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=384 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=640 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=768 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=896 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1024 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1152 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1280 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1408 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1536 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1664 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1792 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1920 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=2048 -aarch64-enable-atomic-cfg-tidy=false < %s 2>%t | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; WARN-NOT: warning
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; Test we can code generater patterns of the form:
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; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
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; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
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;
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; NOTE: Currently shufflevector does not support scalable vectors so it cannot
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; be used to model the above operations. Instead these tests rely on knowing
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; how fixed length operation are lowered to scalable ones, with multiple blocks
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; ensuring insert/extract sequences are not folded away.
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: ptrue
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define void @subvector_v8i32(<8 x i32> *%in, <8 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v8i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
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; CHECK: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; CHECK: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <8 x i32>, <8 x i32>* %in
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br label %bb1
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bb1:
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store <8 x i32> %a, <8 x i32>* %out
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ret void
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}
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define void @subvector_v16i32(<16 x i32> *%in, <16 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v16i32:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
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; VBITS_GE_512: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_512: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECKT: ret
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%a = load <16 x i32>, <16 x i32>* %in
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br label %bb1
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bb1:
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store <16 x i32> %a, <16 x i32>* %out
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ret void
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}
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define void @subvector_v32i32(<32 x i32> *%in, <32 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v32i32:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
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; VBITS_GE_1024: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_1024: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <32 x i32>, <32 x i32>* %in
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br label %bb1
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bb1:
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store <32 x i32> %a, <32 x i32>* %out
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ret void
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}
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define void @subvector_v64i32(<64 x i32> *%in, <64 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v64i32:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
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; VBITS_GE_2048: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_2048: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <64 x i32>, <64 x i32>* %in
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br label %bb1
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bb1:
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store <64 x i32> %a, <64 x i32>* %out
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ret void
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}
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define <8 x i1> @no_warn_dropped_scalable(<8 x i32>* %in) #0 {
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; CHECK-LABEL: no_warn_dropped_scalable:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
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; CHECK: ld1w { [[A:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK: cmpgt p{{[0-9]}}.s, [[PG]]/z, [[A]].s, #0
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; CHECK: ret
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%a = load <8 x i32>, <8 x i32>* %in
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br label %bb1
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bb1:
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%cond = icmp sgt <8 x i32> %a, zeroinitializer
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ret <8 x i1> %cond
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}
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; binop(insert_subvec(a), insert_subvec(b)) -> insert_subvec(binop(a,b)) like
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; combines remove redundant subvector operations. This test ensures it's not
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; performed when the input idiom is the result of operation legalisation. When
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; not prevented the test triggers infinite combine->legalise->combine->...
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define void @no_subvector_binop_hang(<8 x i32>* %in, <8 x i32>* %out, i1 %cond) #0 {
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; CHECK-LABEL: no_subvector_binop_hang:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue [[PG:p[0-9]+]].s, vl8
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; CHECK-NEXT: ld1w { [[A:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-NEXT: ld1w { [[B:z[0-9]+]].s }, [[PG]]/z, [x1]
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; CHECK-NEXT: tbz w2, #0, .LBB5_2
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; CHECK-NEXT: // %bb.1: // %bb.1
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; CHECK-NEXT: orr [[OR:z[0-9]+]].d, [[A]].d, [[B]].d
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; CHECK-NEXT: st1w { [[OR]].s }, [[PG]], [x1]
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; CHECK-NEXT: .LBB5_2: // %bb.2
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; CHECK-NEXT: ret
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%a = load <8 x i32>, <8 x i32>* %in
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%b = load <8 x i32>, <8 x i32>* %out
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br i1 %cond, label %bb.1, label %bb.2
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bb.1:
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%or = or <8 x i32> %a, %b
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store <8 x i32> %or, <8 x i32>* %out
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br label %bb.2
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bb.2:
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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