llvm-for-llvmta/test/CodeGen/AArch64/sve-copy-zprpair.mir

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2022-04-25 10:02:23 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=postrapseudos -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: copy_zpr2
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$z0_z1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $z0_z1
; CHECK-LABEL: name: copy_zpr2
; CHECK: liveins: $z0_z1
; CHECK: $z2 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z0, $z0
; CHECK: $z0 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z2, $z2
; CHECK: RET_ReallyLR
$z1_z2 = COPY $z0_z1
$z0_z1 = COPY $z1_z2
RET_ReallyLR
...
---
name: copy_zpr3
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$z0_z1_z2' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $z0_z1_z2
; CHECK-LABEL: name: copy_zpr3
; CHECK: liveins: $z0_z1_z2
; CHECK: $z3 = ORR_ZZZ $z2, $z2
; CHECK: $z2 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z0, $z0
; CHECK: $z0 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z2, $z2
; CHECK: $z2 = ORR_ZZZ $z3, $z3
; CHECK: RET_ReallyLR
$z1_z2_z3 = COPY $z0_z1_z2
$z0_z1_z2 = COPY $z1_z2_z3
RET_ReallyLR
...
---
name: copy_zpr4
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$z0_z1_z2_z3' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $z0_z1_z2_z3
; CHECK-LABEL: name: copy_zpr4
; CHECK: liveins: $z0_z1_z2_z3
; CHECK: $z4 = ORR_ZZZ $z3, $z3
; CHECK: $z3 = ORR_ZZZ $z2, $z2
; CHECK: $z2 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z0, $z0
; CHECK: $z0 = ORR_ZZZ $z1, $z1
; CHECK: $z1 = ORR_ZZZ $z2, $z2
; CHECK: $z2 = ORR_ZZZ $z3, $z3
; CHECK: $z3 = ORR_ZZZ $z4, $z4
; CHECK: RET_ReallyLR
$z1_z2_z3_z4 = COPY $z0_z1_z2_z3
$z0_z1_z2_z3 = COPY $z1_z2_z3_z4
RET_ReallyLR
...