221 lines
8.9 KiB
LLVM
221 lines
8.9 KiB
LLVM
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; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,ISBDSB,ISBDSBDAGISEL
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; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,SB,SBDAGISEL
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,NOHARDEN
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr,harden-sls-blr -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,ISBDSB
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr,harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,SB
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; Function Attrs: norecurse nounwind readnone
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define dso_local i32 @double_return(i32 %a, i32 %b) local_unnamed_addr {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%div = sdiv i32 %a, %b
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ret i32 %div
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if.else: ; preds = %entry
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%div1 = sdiv i32 %b, %a
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ret i32 %div1
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; CHECK-LABEL: double_return:
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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@__const.indirect_branch.ptr = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@indirect_branch, %return), i8* blockaddress(@indirect_branch, %l2)], align 8
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; Function Attrs: norecurse nounwind readnone
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define dso_local i32 @indirect_branch(i32 %a, i32 %b, i32 %i) {
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; CHECK-LABEL: indirect_branch:
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entry:
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @__const.indirect_branch.ptr, i64 0, i64 %idxprom
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%0 = load i8*, i8** %arrayidx, align 8
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indirectbr i8* %0, [label %return, label %l2]
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; CHECK: br x
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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l2: ; preds = %entry
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br label %return
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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return: ; preds = %entry, %l2
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%retval.0 = phi i32 [ 1, %l2 ], [ 0, %entry ]
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ret i32 %retval.0
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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; Check that RETAA and RETAB instructions are also protected as expected.
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define dso_local i32 @ret_aa(i32 returned %a) local_unnamed_addr "target-features"="+neon,+v8.3a" "sign-return-address"="all" "sign-return-address-key"="a_key" {
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entry:
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; CHECK-LABEL: ret_aa:
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; CHECK: {{ retaa$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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ret i32 %a
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}
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define dso_local i32 @ret_ab(i32 returned %a) local_unnamed_addr "target-features"="+neon,+v8.3a" "sign-return-address"="all" "sign-return-address-key"="b_key" {
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entry:
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; CHECK-LABEL: ret_ab:
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; CHECK: {{ retab$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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ret i32 %a
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}
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define i32 @asmgoto() {
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entry:
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; CHECK-LABEL: asmgoto:
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callbr void asm sideeffect "B $0", "X"(i8* blockaddress(@asmgoto, %d))
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to label %asm.fallthrough [label %d]
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; The asm goto above produces a direct branch:
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; CHECK: //APP
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; CHECK-NEXT: {{^[ \t]+b }}
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; CHECK-NEXT: //NO_APP
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; For direct branches, no mitigation is needed.
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; ISDDSB-NOT: dsb sy
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; SB-NOT: {{ sb$}}
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asm.fallthrough: ; preds = %entry
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ret i32 0
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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d: ; preds = %asm.fallthrough, %entry
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ret i32 1
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; CHECK: {{ret$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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define dso_local i32 @indirect_call(
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i32 (...)* nocapture %f1, i32 (...)* nocapture %f2) {
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entry:
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; CHECK-LABEL: indirect_call:
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%callee.knr.cast = bitcast i32 (...)* %f1 to i32 ()*
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%call = tail call i32 %callee.knr.cast()
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; HARDEN: bl {{__llvm_slsblr_thunk_x[0-9]+$}}
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%callee.knr.cast1 = bitcast i32 (...)* %f2 to i32 ()*
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%call2 = tail call i32 %callee.knr.cast1()
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; HARDEN: bl {{__llvm_slsblr_thunk_x[0-9]+$}}
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%add = add nsw i32 %call2, %call
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ret i32 %add
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; CHECK: .Lfunc_end
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}
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; verify calling through a function pointer.
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@a = dso_local local_unnamed_addr global i32 (...)* null, align 8
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@b = dso_local local_unnamed_addr global i32 0, align 4
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define dso_local void @indirect_call_global() local_unnamed_addr {
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; CHECK-LABEL: indirect_call_global:
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entry:
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%0 = load i32 ()*, i32 ()** bitcast (i32 (...)** @a to i32 ()**), align 8
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%call = tail call i32 %0() nounwind
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; HARDEN: bl {{__llvm_slsblr_thunk_x[0-9]+$}}
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store i32 %call, i32* @b, align 4
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ret void
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; CHECK: .Lfunc_end
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}
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; Verify that neither x16 nor x17 are used when the BLR mitigation is enabled,
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; as a linker is allowed to clobber x16 or x17 on calls, which would break the
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; correct execution of the code sequence produced by the mitigation.
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; The below test carefully increases register pressure to persuade code
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; generation to produce a BLR x16. Yes, that is a bit fragile.
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define i64 @check_x16(i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp, i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp2) "target-features"="+neon,+reserve-x10,+reserve-x11,+reserve-x12,+reserve-x13,+reserve-x14,+reserve-x15,+reserve-x18,+reserve-x20,+reserve-x21,+reserve-x22,+reserve-x23,+reserve-x24,+reserve-x25,+reserve-x26,+reserve-x27,+reserve-x28,+reserve-x30,+reserve-x9" {
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entry:
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; CHECK-LABEL: check_x16:
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%0 = load i64 (i8*, i64, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** %fp, align 8
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%1 = bitcast i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** %fp2 to i8**
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%2 = load i8*, i8** %1, align 8
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%call = call i64 %0(i8* %2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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%3 = load i64 (i8*, i64, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** %fp2, align 8
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%4 = bitcast i64 (i8*, i64, i64, i64, i64, i64, i64, i64)** %fp to i8**
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%5 = load i8*, i8** %4, align 8;, !tbaa !2
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%call1 = call i64 %3(i8* %5, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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; NOHARDEN: blr x16
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; ISBDSB-NOT: bl __llvm_slsblr_thunk_x16
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; SB-NOT: bl __llvm_slsblr_thunk_x16
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; CHECK
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%add = add nsw i64 %call1, %call
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ret i64 %add
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; CHECK: .Lfunc_end
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}
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; Verify that the transformation works correctly for x29 when it is not
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; reserved to be used as a frame pointer.
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; Since this is sensitive to register allocation choices, only check this with
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; DAGIsel to avoid too much accidental breaking of this test that is a bit
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; brittle.
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define i64 @check_x29(i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp,
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i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp2,
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i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp3)
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"target-features"="+neon,+reserve-x10,+reserve-x11,+reserve-x12,+reserve-x13,+reserve-x14,+reserve-x15,+reserve-x18,+reserve-x20,+reserve-x21,+reserve-x22,+reserve-x23,+reserve-x24,+reserve-x25,+reserve-x26,+reserve-x27,+reserve-x28,+reserve-x9"
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"frame-pointer"="none"
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{
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entry:
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; CHECK-LABEL: check_x29:
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%0 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp, align 8
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%1 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp2 to i8**
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%2 = load i8*, i8** %1, align 8
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%3 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp2, align 8
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%4 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp3 to i8**
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%5 = load i8*, i8** %4, align 8
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%6 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp3, align 8
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%7 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp to i8**
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%8 = load i8*, i8** %7, align 8
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%call = call i64 %0(i8* %2, i8* %5, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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%call1 = call i64 %3(i8* %2, i8* %5, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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; NOHARDEN: blr x29
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; ISBDSBDAGISEL: bl __llvm_slsblr_thunk_x29
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; SBDAGISEL: bl __llvm_slsblr_thunk_x29
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; CHECK
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%call2 = call i64 %6(i8* %2, i8* %8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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%add = add nsw i64 %call1, %call
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%add1 = add nsw i64 %call2, %add
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ret i64 %add1
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; CHECK: .Lfunc_end
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}
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; HARDEN-label: __llvm_slsblr_thunk_x0:
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; HARDEN: mov x16, x0
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; HARDEN: br x16
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: dsb sy
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; SB-NEXT: isb
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; HARDEN-NEXT: .Lfunc_end
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; HARDEN-label: __llvm_slsblr_thunk_x19:
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; HARDEN: mov x16, x19
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; HARDEN: br x16
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: dsb sy
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; SB-NEXT: isb
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; HARDEN-NEXT: .Lfunc_end
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