llvm-for-llvmta/test/CodeGen/AArch64/rmif-def-nzcv.mir

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2022-04-25 10:02:23 +02:00
# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
# CHECK: [[@LINE+10]]:49: missing implicit register operand 'implicit $nzcv'
...
---
name: test_flags
liveins:
- { reg: '$x0' }
body: |
bb.0:
liveins: $x0
RMIF renamable $x0, 0, 0, implicit-def $nzcv
RET undef $lr, implicit killed $w0