359 lines
8.5 KiB
LLVM
359 lines
8.5 KiB
LLVM
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s
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declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtns.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtns.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtms.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtms.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtau.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtau.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtas.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtas.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half)
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declare i64 @llvm.aarch64.neon.fcvtzu.i64.f16(half)
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declare i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half)
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declare half @llvm.aarch64.neon.frsqrte.f16(half)
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declare half @llvm.aarch64.neon.frecpx.f16(half)
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declare half @llvm.aarch64.neon.frecpe.f16(half)
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define dso_local i16 @t2(half %a) {
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; CHECK-LABEL: t2:
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; CHECK: fcmp h0, #0.0
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; CHECK-NEXT: csetm w0, eq
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oeq half %a, 0xH0000
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%vceqz = sext i1 %0 to i16
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ret i16 %vceqz
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}
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define dso_local i16 @t3(half %a) {
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; CHECK-LABEL: t3:
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; CHECK: fcmp h0, #0.0
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; CHECK-NEXT: csetm w0, ge
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oge half %a, 0xH0000
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%vcgez = sext i1 %0 to i16
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ret i16 %vcgez
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}
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define dso_local i16 @t4(half %a) {
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; CHECK-LABEL: t4:
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; CHECK: fcmp h0, #0.0
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; CHECK-NEXT: csetm w0, gt
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ogt half %a, 0xH0000
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%vcgtz = sext i1 %0 to i16
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ret i16 %vcgtz
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}
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define dso_local i16 @t5(half %a) {
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; CHECK-LABEL: t5:
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; CHECK: fcmp h0, #0.0
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; CHECK-NEXT: csetm w0, ls
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ole half %a, 0xH0000
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%vclez = sext i1 %0 to i16
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ret i16 %vclez
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}
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define dso_local i16 @t6(half %a) {
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; CHECK-LABEL: t6:
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; CHECK: fcmp h0, #0.0
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; CHECK-NEXT: csetm w0, mi
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp olt half %a, 0xH0000
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%vcltz = sext i1 %0 to i16
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ret i16 %vcltz
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}
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define dso_local half @t8(i32 %a) {
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; CHECK-LABEL: t8:
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; CHECK: scvtf h0, w0
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; CHECK-NEXT: ret
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entry:
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%0 = sitofp i32 %a to half
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ret half %0
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}
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define dso_local half @t9(i64 %a) {
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; CHECK-LABEL: t9:
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; CHECK: scvtf h0, x0
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; CHECK-NEXT: ret
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entry:
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%0 = sitofp i64 %a to half
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ret half %0
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}
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define dso_local half @t12(i64 %a) {
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; CHECK-LABEL: t12:
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; CHECK: ucvtf h0, x0
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; CHECK-NEXT: ret
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entry:
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%0 = uitofp i64 %a to half
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ret half %0
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}
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define dso_local i16 @t13(half %a) {
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; CHECK-LABEL: t13:
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; CHECK: fcvtzs w0, h0
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; CHECK-NEXT: ret
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entry:
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%0 = fptosi half %a to i16
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ret i16 %0
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}
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define dso_local i64 @t15(half %a) {
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; CHECK-LABEL: t15:
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; CHECK: fcvtzs x0, h0
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; CHECK-NEXT: ret
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entry:
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%0 = fptosi half %a to i64
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ret i64 %0
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}
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define dso_local i16 @t16(half %a) {
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; CHECK-LABEL: t16:
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; CHECK: fcvtzs w0, h0
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; CHECK-NEXT: ret
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entry:
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%0 = fptoui half %a to i16
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ret i16 %0
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}
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define dso_local i64 @t18(half %a) {
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; CHECK-LABEL: t18:
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; CHECK: fcvtzu x0, h0
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; CHECK-NEXT: ret
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entry:
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%0 = fptoui half %a to i64
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ret i64 %0
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}
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define i32 @fcvtzu_intrinsic_i32(half %a) {
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; CHECK-LABEL: fcvtzu_intrinsic_i32:
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; CHECK: fcvtzu w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half %a)
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ret i32 %fcvt
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}
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define i64 @fcvtzu_intrinsic_i64(half %a) {
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; CHECK-LABEL: fcvtzu_intrinsic_i64:
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; CHECK: fcvtzs x0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
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ret i64 %fcvt
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}
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define i32 @fcvtzs_intrinsic_i32(half %a) {
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; CHECK-LABEL: fcvtzs_intrinsic_i32:
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; CHECK: fcvtzs w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a)
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ret i32 %fcvt
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}
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define i64 @fcvtzs_intrinsic_i64(half %a) {
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; CHECK-LABEL: fcvtzs_intrinsic_i64:
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; CHECK: fcvtzs x0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
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ret i64 %fcvt
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}
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define dso_local i16 @t19(half %a) {
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; CHECK-LABEL: t19:
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; CHECK: fcvtas w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t21(half %a) {
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; CHECK-LABEL: t21:
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; CHECK: fcvtas x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)
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ret i64 %vcvtah_s64_f16
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}
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define dso_local i16 @t22(half %a) {
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; CHECK-LABEL: t22:
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; CHECK: fcvtau w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t24(half %a) {
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; CHECK-LABEL: t24:
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; CHECK: fcvtau x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtah_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)
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ret i64 %vcvtah_u64_f16
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}
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define dso_local i16 @t25(half %a) {
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; CHECK-LABEL: t25:
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; CHECK: fcvtms w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t27(half %a) {
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; CHECK-LABEL: t27:
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; CHECK: fcvtms x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtmh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a)
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ret i64 %vcvtmh_s64_f16
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}
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define dso_local i16 @t28(half %a) {
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; CHECK-LABEL: t28:
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; CHECK: fcvtmu w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t30(half %a) {
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; CHECK-LABEL: t30:
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; CHECK: fcvtmu x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtmh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a)
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ret i64 %vcvtmh_u64_f16
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}
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define dso_local i16 @t31(half %a) {
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; CHECK-LABEL: t31:
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; CHECK: fcvtns w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t33(half %a) {
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; CHECK-LABEL: t33:
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; CHECK: fcvtns x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtnh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a)
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ret i64 %vcvtnh_s64_f16
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}
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define dso_local i16 @t34(half %a) {
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; CHECK-LABEL: t34:
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; CHECK: fcvtnu w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t36(half %a) {
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; CHECK-LABEL: t36:
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; CHECK: fcvtnu x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtnh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)
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ret i64 %vcvtnh_u64_f16
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}
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define dso_local i16 @t37(half %a) {
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; CHECK-LABEL: t37:
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; CHECK: fcvtps w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t39(half %a) {
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; CHECK-LABEL: t39:
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; CHECK: fcvtps x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtph_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)
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ret i64 %vcvtph_s64_f16
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}
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define dso_local i16 @t40(half %a) {
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; CHECK-LABEL: t40:
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; CHECK: fcvtpu w0, h0
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; CHECK-NEXT: ret
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entry:
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%fcvt = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half %a)
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%0 = trunc i32 %fcvt to i16
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ret i16 %0
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}
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define dso_local i64 @t42(half %a) {
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; CHECK-LABEL: t42:
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; CHECK: fcvtpu x0, h0
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; CHECK-NEXT: ret
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entry:
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%vcvtph_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a)
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ret i64 %vcvtph_u64_f16
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}
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define dso_local half @t44(half %a) {
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; CHECK-LABEL: t44:
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; CHECK: frecpe h0, h0
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; CHECK-NEXT: ret
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entry:
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%vrecpeh_f16 = tail call half @llvm.aarch64.neon.frecpe.f16(half %a)
|
||
|
|
ret half %vrecpeh_f16
|
||
|
|
}
|
||
|
|
|
||
|
|
define dso_local half @t45(half %a) {
|
||
|
|
; CHECK-LABEL: t45:
|
||
|
|
; CHECK: frecpx h0, h0
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
entry:
|
||
|
|
%vrecpxh_f16 = tail call half @llvm.aarch64.neon.frecpx.f16(half %a)
|
||
|
|
ret half %vrecpxh_f16
|
||
|
|
}
|
||
|
|
|
||
|
|
define dso_local half @t53(half %a) {
|
||
|
|
; CHECK-LABEL: t53:
|
||
|
|
; CHECK: frsqrte h0, h0
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
entry:
|
||
|
|
%vrsqrteh_f16 = tail call half @llvm.aarch64.neon.frsqrte.f16(half %a)
|
||
|
|
ret half %vrsqrteh_f16
|
||
|
|
}
|