91 lines
2.8 KiB
Plaintext
91 lines
2.8 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: add_v16s8
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v16s8
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16)
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; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16)
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%2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
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%3:_(s32) = G_ANYEXT %2(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v8s16
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v8s16
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16)
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; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16)
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%2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
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%3:_(s32) = G_ANYEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v4s32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v4s32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16)
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; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
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; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
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%2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_v2s64
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_v2s64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16)
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; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
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; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%1:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
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%2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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