257 lines
10 KiB
C
257 lines
10 KiB
C
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//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// X86 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class InstCombiner;
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class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
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typedef BasicTTIImplBase<X86TTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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const X86Subtarget *getST() const { return ST; }
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const X86TargetLowering *getTLI() const { return TLI; }
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const FeatureBitset InlineFeatureIgnoreList = {
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// This indicates the CPU is 64 bit capable not that we are in 64-bit
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// mode.
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X86::Feature64Bit,
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// These features don't have any intrinsics or ABI effect.
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X86::FeatureNOPL,
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X86::FeatureCMPXCHG16B,
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X86::FeatureLAHFSAHF,
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// Codegen control options.
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X86::FeatureFast11ByteNOP,
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X86::FeatureFast15ByteNOP,
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X86::FeatureFastBEXTR,
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X86::FeatureFastHorizontalOps,
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X86::FeatureFastLZCNT,
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X86::FeatureFastScalarFSQRT,
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X86::FeatureFastSHLDRotate,
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X86::FeatureFastScalarShiftMasks,
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X86::FeatureFastVectorShiftMasks,
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X86::FeatureFastVariableShuffle,
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X86::FeatureFastVectorFSQRT,
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X86::FeatureLEAForSP,
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X86::FeatureLEAUsesAG,
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X86::FeatureLZCNTFalseDeps,
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X86::FeatureBranchFusion,
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X86::FeatureMacroFusion,
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X86::FeaturePadShortFunctions,
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X86::FeaturePOPCNTFalseDeps,
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X86::FeatureSSEUnalignedMem,
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X86::FeatureSlow3OpsLEA,
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X86::FeatureSlowDivide32,
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X86::FeatureSlowDivide64,
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X86::FeatureSlowIncDec,
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X86::FeatureSlowLEA,
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X86::FeatureSlowPMADDWD,
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X86::FeatureSlowPMULLD,
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X86::FeatureSlowSHLD,
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X86::FeatureSlowTwoMemOps,
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X86::FeatureSlowUAMem16,
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X86::FeaturePreferMaskRegisters,
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X86::FeatureInsertVZEROUPPER,
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X86::FeatureUseGLMDivSqrtCosts,
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// Perf-tuning flags.
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X86::FeatureHasFastGather,
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X86::FeatureSlowUAMem32,
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// Based on whether user set the -mprefer-vector-width command line.
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X86::FeaturePrefer128Bit,
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X86::FeaturePrefer256Bit,
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// CPU name enums. These just follow CPU string.
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X86::ProcIntelAtom,
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X86::ProcIntelSLM,
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};
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public:
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explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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/// \name Cache TTI Implementation
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/// @{
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llvm::Optional<unsigned> getCacheSize(
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TargetTransformInfo::CacheLevel Level) const override;
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llvm::Optional<unsigned> getCacheAssociativity(
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TargetTransformInfo::CacheLevel Level) const override;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(unsigned ClassID) const;
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index,
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VectorType *SubTp);
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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CmpInst::Predicate VecPred,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
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bool Insert, bool Extract);
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int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getMaskedMemoryOpCost(
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unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency);
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int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
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bool VariableMask, Align Alignment,
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TTI::TargetCostKind CostKind,
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const Instruction *I);
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int getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
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const SCEV *Ptr);
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Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const;
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Optional<Value *>
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simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
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APInt DemandedMask, KnownBits &Known,
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bool &KnownBitsComputed) const;
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Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const;
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unsigned getAtomicMemIntrinsicMaxElementSize() const;
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int getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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int getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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bool IsPairwiseForm,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency);
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int getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
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int getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsPairwiseForm, bool IsUnsigned,
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TTI::TargetCostKind CostKind);
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int getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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int getInterleavedMemoryOpCostAVX512(
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unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
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ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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int getInterleavedMemoryOpCostAVX2(
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unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
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ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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int getIntImmCost(int64_t);
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int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
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unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind);
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int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr);
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int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind);
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bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
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TargetTransformInfo::LSRCost &C2);
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bool canMacroFuseCmp();
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bool isLegalMaskedLoad(Type *DataType, Align Alignment);
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bool isLegalMaskedStore(Type *DataType, Align Alignment);
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bool isLegalNTLoad(Type *DataType, Align Alignment);
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bool isLegalNTStore(Type *DataType, Align Alignment);
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bool isLegalMaskedGather(Type *DataType, Align Alignment);
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bool isLegalMaskedScatter(Type *DataType, Align Alignment);
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bool isLegalMaskedExpandLoad(Type *DataType);
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bool isLegalMaskedCompressStore(Type *DataType);
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bool hasDivRemOp(Type *DataType, bool IsSigned);
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bool isFCmpOrdCheaperThanFCmpZero(Type *Ty);
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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bool areFunctionArgsABICompatible(const Function *Caller,
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const Function *Callee,
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SmallPtrSetImpl<Argument *> &Args) const;
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TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
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bool IsZeroCmp) const;
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bool enableInterleavedAccessVectorization();
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/// Allow vectorizers to form reduction intrinsics in IR. The IR is expanded
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/// into shuffles and vector math/logic by the backend
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/// (see TTI::shouldExpandReduction)
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bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const {
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return true;
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}
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private:
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int getGSScalarCost(unsigned Opcode, Type *DataTy, bool VariableMask,
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Align Alignment, unsigned AddressSpace);
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int getGSVectorCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
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Align Alignment, unsigned AddressSpace);
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int getGatherOverhead() const;
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int getScatterOverhead() const;
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/// @}
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};
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} // end namespace llvm
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#endif
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