30 lines
1.1 KiB
TableGen
30 lines
1.1 KiB
TableGen
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//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel SGX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SGX instructions
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let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
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// ENCLS - Execute an Enclave System Function of Specified Leaf Number
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def ENCLS : I<0x01, MRM_CF, (outs), (ins),
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"encls", []>, PS;
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// ENCLU - Execute an Enclave User Function of Specified Leaf Number
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def ENCLU : I<0x01, MRM_D7, (outs), (ins),
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"enclu", []>, PS;
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// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number
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def ENCLV : I<0x01, MRM_C0, (outs), (ins),
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"enclv", []>, PS;
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} // SchedRW
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