540 lines
19 KiB
C++
540 lines
19 KiB
C++
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//===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, other late
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// optimizations, or simply the encoding of the instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86FrameLowering.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/Analysis/EHPersonalities.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
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#include "llvm/IR/GlobalValue.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-pseudo"
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#define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
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namespace {
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class X86ExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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X86ExpandPseudo() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const X86Subtarget *STI = nullptr;
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const X86InstrInfo *TII = nullptr;
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const X86RegisterInfo *TRI = nullptr;
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const X86MachineFunctionInfo *X86FI = nullptr;
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const X86FrameLowering *X86FL = nullptr;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override {
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return "X86 pseudo instruction expansion pass";
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}
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private:
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void ExpandICallBranchFunnel(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MBBI);
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bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool ExpandMBB(MachineBasicBlock &MBB);
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};
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char X86ExpandPseudo::ID = 0;
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} // End anonymous namespace.
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INITIALIZE_PASS(X86ExpandPseudo, DEBUG_TYPE, X86_EXPAND_PSEUDO_NAME, false,
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false)
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void X86ExpandPseudo::ExpandICallBranchFunnel(
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MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI) {
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MachineBasicBlock *JTMBB = MBB;
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MachineInstr *JTInst = &*MBBI;
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MachineFunction *MF = MBB->getParent();
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const BasicBlock *BB = MBB->getBasicBlock();
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auto InsPt = MachineFunction::iterator(MBB);
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++InsPt;
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std::vector<std::pair<MachineBasicBlock *, unsigned>> TargetMBBs;
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DebugLoc DL = JTInst->getDebugLoc();
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MachineOperand Selector = JTInst->getOperand(0);
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const GlobalValue *CombinedGlobal = JTInst->getOperand(1).getGlobal();
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auto CmpTarget = [&](unsigned Target) {
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if (Selector.isReg())
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MBB->addLiveIn(Selector.getReg());
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BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
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.addReg(X86::RIP)
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.addImm(1)
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.addReg(0)
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.addGlobalAddress(CombinedGlobal,
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JTInst->getOperand(2 + 2 * Target).getImm())
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.addReg(0);
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BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
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.add(Selector)
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.addReg(X86::R11);
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};
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auto CreateMBB = [&]() {
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auto *NewMBB = MF->CreateMachineBasicBlock(BB);
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MBB->addSuccessor(NewMBB);
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if (!MBB->isLiveIn(X86::EFLAGS))
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MBB->addLiveIn(X86::EFLAGS);
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return NewMBB;
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};
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auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
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BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
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auto *ElseMBB = CreateMBB();
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MF->insert(InsPt, ElseMBB);
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MBB = ElseMBB;
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MBBI = MBB->end();
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};
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auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
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auto *ThenMBB = CreateMBB();
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TargetMBBs.push_back({ThenMBB, Target});
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EmitCondJump(CC, ThenMBB);
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};
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auto EmitTailCall = [&](unsigned Target) {
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BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
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.add(JTInst->getOperand(3 + 2 * Target));
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};
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std::function<void(unsigned, unsigned)> EmitBranchFunnel =
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[&](unsigned FirstTarget, unsigned NumTargets) {
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if (NumTargets == 1) {
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EmitTailCall(FirstTarget);
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return;
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}
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if (NumTargets == 2) {
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CmpTarget(FirstTarget + 1);
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EmitCondJumpTarget(X86::COND_B, FirstTarget);
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EmitTailCall(FirstTarget + 1);
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return;
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}
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if (NumTargets < 6) {
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CmpTarget(FirstTarget + 1);
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EmitCondJumpTarget(X86::COND_B, FirstTarget);
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EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
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EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
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return;
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}
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auto *ThenMBB = CreateMBB();
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CmpTarget(FirstTarget + (NumTargets / 2));
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EmitCondJump(X86::COND_B, ThenMBB);
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EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
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EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
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NumTargets - (NumTargets / 2) - 1);
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MF->insert(InsPt, ThenMBB);
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MBB = ThenMBB;
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MBBI = MBB->end();
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EmitBranchFunnel(FirstTarget, NumTargets / 2);
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};
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EmitBranchFunnel(0, (JTInst->getNumOperands() - 2) / 2);
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for (auto P : TargetMBBs) {
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MF->insert(InsPt, P.first);
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BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
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.add(JTInst->getOperand(3 + 2 * P.second));
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}
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JTMBB->erase(JTInst);
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}
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/// If \p MBBI is a pseudo instruction, this method expands
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/// it to the corresponding (sequence of) actual instruction(s).
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/// \returns true if \p MBBI has been expanded.
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bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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switch (Opcode) {
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default:
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return false;
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case X86::TCRETURNdi:
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case X86::TCRETURNdicc:
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case X86::TCRETURNri:
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case X86::TCRETURNmi:
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case X86::TCRETURNdi64:
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case X86::TCRETURNdi64cc:
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case X86::TCRETURNri64:
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case X86::TCRETURNmi64: {
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bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
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: 1);
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assert(StackAdjust.isImm() && "Expecting immediate value.");
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// Adjust stack pointer.
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int StackAdj = StackAdjust.getImm();
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int MaxTCDelta = X86FI->getTCReturnAddrDelta();
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int Offset = 0;
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assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
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// Incoporate the retaddr area.
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Offset = StackAdj - MaxTCDelta;
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assert(Offset >= 0 && "Offset should never be negative");
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if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
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assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
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}
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if (Offset) {
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// Check for possible merge with preceding ADD instruction.
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Offset += X86FL->mergeSPUpdates(MBB, MBBI, true);
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X86FL->emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue=*/true);
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}
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// Jump to label or value in register.
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bool IsWin64 = STI->isTargetWin64();
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if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
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Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
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unsigned Op;
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switch (Opcode) {
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case X86::TCRETURNdi:
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Op = X86::TAILJMPd;
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break;
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case X86::TCRETURNdicc:
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Op = X86::TAILJMPd_CC;
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break;
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case X86::TCRETURNdi64cc:
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assert(!MBB.getParent()->hasWinCFI() &&
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"Conditional tail calls confuse "
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"the Win64 unwinder.");
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Op = X86::TAILJMPd64_CC;
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break;
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default:
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// Note: Win64 uses REX prefixes indirect jumps out of functions, but
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// not direct ones.
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Op = X86::TAILJMPd64;
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break;
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}
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
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if (JumpTarget.isGlobal()) {
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MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else {
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assert(JumpTarget.isSymbol());
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MIB.addExternalSymbol(JumpTarget.getSymbolName(),
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JumpTarget.getTargetFlags());
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}
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if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
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MIB.addImm(MBBI->getOperand(2).getImm());
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}
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} else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
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unsigned Op = (Opcode == X86::TCRETURNmi)
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? X86::TAILJMPm
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: (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
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for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
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MIB.add(MBBI->getOperand(i));
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} else if (Opcode == X86::TCRETURNri64) {
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JumpTarget.setIsKill();
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BuildMI(MBB, MBBI, DL,
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TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
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.add(JumpTarget);
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} else {
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JumpTarget.setIsKill();
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BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
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.add(JumpTarget);
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}
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MachineInstr &NewMI = *std::prev(MBBI);
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NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
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// Update the call site info.
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if (MBBI->isCandidateForCallSiteEntry())
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MBB.getParent()->moveCallSiteInfo(&*MBBI, &NewMI);
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// Delete the pseudo instruction TCRETURN.
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MBB.erase(MBBI);
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return true;
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}
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case X86::EH_RETURN:
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case X86::EH_RETURN64: {
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MachineOperand &DestAddr = MBBI->getOperand(0);
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assert(DestAddr.isReg() && "Offset should be in register!");
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const bool Uses64BitFramePtr =
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STI->isTarget64BitLP64() || STI->isTargetNaCl64();
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Register StackPtr = TRI->getStackRegister();
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BuildMI(MBB, MBBI, DL,
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TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
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.addReg(DestAddr.getReg());
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// The EH_RETURN pseudo is really removed during the MC Lowering.
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return true;
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}
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case X86::IRET: {
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// Adjust stack to erase error code
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int64_t StackAdj = MBBI->getOperand(0).getImm();
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X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
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// Replace pseudo with machine iret
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BuildMI(MBB, MBBI, DL,
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TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
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MBB.erase(MBBI);
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return true;
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}
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case X86::RET: {
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// Adjust stack to erase error code
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int64_t StackAdj = MBBI->getOperand(0).getImm();
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MachineInstrBuilder MIB;
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if (StackAdj == 0) {
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MIB = BuildMI(MBB, MBBI, DL,
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TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
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} else if (isUInt<16>(StackAdj)) {
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MIB = BuildMI(MBB, MBBI, DL,
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TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
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.addImm(StackAdj);
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} else {
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assert(!STI->is64Bit() &&
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"shouldn't need to do this for x86_64 targets!");
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// A ret can only handle immediates as big as 2**16-1. If we need to pop
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// off bytes before the return address, we must do it manually.
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BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
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X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
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BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
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MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
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}
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for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
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MIB.add(MBBI->getOperand(I));
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MBB.erase(MBBI);
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return true;
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}
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case X86::LCMPXCHG16B_SAVE_RBX: {
|
||
|
|
// Perform the following transformation.
|
||
|
|
// SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
|
||
|
|
// =>
|
||
|
|
// RBX = InArg
|
||
|
|
// actualcmpxchg Addr
|
||
|
|
// RBX = SaveRbx
|
||
|
|
const MachineOperand &InArg = MBBI->getOperand(6);
|
||
|
|
Register SaveRbx = MBBI->getOperand(7).getReg();
|
||
|
|
|
||
|
|
// Copy the input argument of the pseudo into the argument of the
|
||
|
|
// actual instruction.
|
||
|
|
// NOTE: We don't copy the kill flag since the input might be the same reg
|
||
|
|
// as one of the other operands of LCMPXCHG16B.
|
||
|
|
TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false);
|
||
|
|
// Create the actual instruction.
|
||
|
|
MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(X86::LCMPXCHG16B));
|
||
|
|
// Copy the operands related to the address.
|
||
|
|
for (unsigned Idx = 1; Idx < 6; ++Idx)
|
||
|
|
NewInstr->addOperand(MBBI->getOperand(Idx));
|
||
|
|
// Finally, restore the value of RBX.
|
||
|
|
TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx,
|
||
|
|
/*SrcIsKill*/ true);
|
||
|
|
|
||
|
|
// Delete the pseudo.
|
||
|
|
MBBI->eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
// Loading/storing mask pairs requires two kmov operations. The second one of
|
||
|
|
// these needs a 2 byte displacement relative to the specified address (with
|
||
|
|
// 32 bit spill size). The pairs of 1bit masks up to 16 bit masks all use the
|
||
|
|
// same spill size, they all are stored using MASKPAIR16STORE, loaded using
|
||
|
|
// MASKPAIR16LOAD.
|
||
|
|
//
|
||
|
|
// The displacement value might wrap around in theory, thus the asserts in
|
||
|
|
// both cases.
|
||
|
|
case X86::MASKPAIR16LOAD: {
|
||
|
|
int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
|
||
|
|
assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
|
||
|
|
Register Reg = MBBI->getOperand(0).getReg();
|
||
|
|
bool DstIsDead = MBBI->getOperand(0).isDead();
|
||
|
|
Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
|
||
|
|
Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
|
||
|
|
|
||
|
|
auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
|
||
|
|
.addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead));
|
||
|
|
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWkm))
|
||
|
|
.addReg(Reg1, RegState::Define | getDeadRegState(DstIsDead));
|
||
|
|
|
||
|
|
for (int i = 0; i < X86::AddrNumOperands; ++i) {
|
||
|
|
MIBLo.add(MBBI->getOperand(1 + i));
|
||
|
|
if (i == X86::AddrDisp)
|
||
|
|
MIBHi.addImm(Disp + 2);
|
||
|
|
else
|
||
|
|
MIBHi.add(MBBI->getOperand(1 + i));
|
||
|
|
}
|
||
|
|
|
||
|
|
// Split the memory operand, adjusting the offset and size for the halves.
|
||
|
|
MachineMemOperand *OldMMO = MBBI->memoperands().front();
|
||
|
|
MachineFunction *MF = MBB.getParent();
|
||
|
|
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
|
||
|
|
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
|
||
|
|
|
||
|
|
MIBLo.setMemRefs(MMOLo);
|
||
|
|
MIBHi.setMemRefs(MMOHi);
|
||
|
|
|
||
|
|
// Delete the pseudo.
|
||
|
|
MBB.erase(MBBI);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::MASKPAIR16STORE: {
|
||
|
|
int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
|
||
|
|
assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
|
||
|
|
Register Reg = MBBI->getOperand(X86::AddrNumOperands).getReg();
|
||
|
|
bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill();
|
||
|
|
Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0);
|
||
|
|
Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1);
|
||
|
|
|
||
|
|
auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
|
||
|
|
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(X86::KMOVWmk));
|
||
|
|
|
||
|
|
for (int i = 0; i < X86::AddrNumOperands; ++i) {
|
||
|
|
MIBLo.add(MBBI->getOperand(i));
|
||
|
|
if (i == X86::AddrDisp)
|
||
|
|
MIBHi.addImm(Disp + 2);
|
||
|
|
else
|
||
|
|
MIBHi.add(MBBI->getOperand(i));
|
||
|
|
}
|
||
|
|
MIBLo.addReg(Reg0, getKillRegState(SrcIsKill));
|
||
|
|
MIBHi.addReg(Reg1, getKillRegState(SrcIsKill));
|
||
|
|
|
||
|
|
// Split the memory operand, adjusting the offset and size for the halves.
|
||
|
|
MachineMemOperand *OldMMO = MBBI->memoperands().front();
|
||
|
|
MachineFunction *MF = MBB.getParent();
|
||
|
|
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 2);
|
||
|
|
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 2, 2);
|
||
|
|
|
||
|
|
MIBLo.setMemRefs(MMOLo);
|
||
|
|
MIBHi.setMemRefs(MMOHi);
|
||
|
|
|
||
|
|
// Delete the pseudo.
|
||
|
|
MBB.erase(MBBI);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::MWAITX_SAVE_RBX: {
|
||
|
|
// Perform the following transformation.
|
||
|
|
// SaveRbx = pseudomwaitx InArg, SaveRbx
|
||
|
|
// =>
|
||
|
|
// [E|R]BX = InArg
|
||
|
|
// actualmwaitx
|
||
|
|
// [E|R]BX = SaveRbx
|
||
|
|
const MachineOperand &InArg = MBBI->getOperand(1);
|
||
|
|
// Copy the input argument of the pseudo into the argument of the
|
||
|
|
// actual instruction.
|
||
|
|
TII->copyPhysReg(MBB, MBBI, DL, X86::EBX, InArg.getReg(), InArg.isKill());
|
||
|
|
// Create the actual instruction.
|
||
|
|
BuildMI(MBB, MBBI, DL, TII->get(X86::MWAITXrrr));
|
||
|
|
// Finally, restore the value of RBX.
|
||
|
|
Register SaveRbx = MBBI->getOperand(2).getReg();
|
||
|
|
TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true);
|
||
|
|
// Delete the pseudo.
|
||
|
|
MBBI->eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case TargetOpcode::ICALL_BRANCH_FUNNEL:
|
||
|
|
ExpandICallBranchFunnel(&MBB, MBBI);
|
||
|
|
return true;
|
||
|
|
case X86::PLDTILECFG: {
|
||
|
|
MI.RemoveOperand(0);
|
||
|
|
MI.setDesc(TII->get(X86::LDTILECFG));
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::PSTTILECFG: {
|
||
|
|
MI.RemoveOperand(MI.getNumOperands() - 1); // Remove $tmmcfg
|
||
|
|
MI.setDesc(TII->get(X86::STTILECFG));
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::PTILELOADDV: {
|
||
|
|
MI.RemoveOperand(8); // Remove $tmmcfg
|
||
|
|
for (unsigned i = 2; i > 0; --i)
|
||
|
|
MI.RemoveOperand(i);
|
||
|
|
MI.setDesc(TII->get(X86::TILELOADD));
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::PTDPBSSDV: {
|
||
|
|
MI.RemoveOperand(7); // Remove $tmmcfg
|
||
|
|
MI.untieRegOperand(4);
|
||
|
|
for (unsigned i = 3; i > 0; --i)
|
||
|
|
MI.RemoveOperand(i);
|
||
|
|
MI.setDesc(TII->get(X86::TDPBSSD));
|
||
|
|
MI.tieOperands(0, 1);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::PTILESTOREDV: {
|
||
|
|
MI.RemoveOperand(8); // Remove $tmmcfg
|
||
|
|
for (int i = 1; i >= 0; --i)
|
||
|
|
MI.RemoveOperand(i);
|
||
|
|
MI.setDesc(TII->get(X86::TILESTORED));
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case X86::PTILEZEROV: {
|
||
|
|
for (int i = 3; i > 0; --i) // Remove row, col, $tmmcfg
|
||
|
|
MI.RemoveOperand(i);
|
||
|
|
MI.setDesc(TII->get(X86::TILEZERO));
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
llvm_unreachable("Previous switch has a fallthrough?");
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Expand all pseudo instructions contained in \p MBB.
|
||
|
|
/// \returns true if any expansion occurred for \p MBB.
|
||
|
|
bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
|
||
|
|
bool Modified = false;
|
||
|
|
|
||
|
|
// MBBI may be invalidated by the expansion.
|
||
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
||
|
|
while (MBBI != E) {
|
||
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
||
|
|
Modified |= ExpandMI(MBB, MBBI);
|
||
|
|
MBBI = NMBBI;
|
||
|
|
}
|
||
|
|
|
||
|
|
return Modified;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
|
||
|
|
STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
|
||
|
|
TII = STI->getInstrInfo();
|
||
|
|
TRI = STI->getRegisterInfo();
|
||
|
|
X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
||
|
|
X86FL = STI->getFrameLowering();
|
||
|
|
|
||
|
|
bool Modified = false;
|
||
|
|
for (MachineBasicBlock &MBB : MF)
|
||
|
|
Modified |= ExpandMBB(MBB);
|
||
|
|
return Modified;
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Returns an instance of the pseudo instruction expansion pass.
|
||
|
|
FunctionPass *llvm::createX86ExpandPseudoPass() {
|
||
|
|
return new X86ExpandPseudo();
|
||
|
|
}
|