273 lines
10 KiB
C++
273 lines
10 KiB
C++
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//==---- SystemZPostRewrite.cpp - Select pseudos after RegAlloc ---*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that is run immediately after VirtRegRewriter
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// but before MachineCopyPropagation. The purpose is to lower pseudos to
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// target instructions before any later pass might substitute a register for
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// another.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#define SYSTEMZ_POSTREWRITE_NAME "SystemZ Post Rewrite pass"
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#define DEBUG_TYPE "systemz-postrewrite"
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STATISTIC(MemFoldCopies, "Number of copies inserted before folded mem ops.");
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STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
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namespace llvm {
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void initializeSystemZPostRewritePass(PassRegistry&);
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}
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namespace {
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class SystemZPostRewrite : public MachineFunctionPass {
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public:
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static char ID;
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SystemZPostRewrite() : MachineFunctionPass(ID) {
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initializeSystemZPostRewritePass(*PassRegistry::getPassRegistry());
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}
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const SystemZInstrInfo *TII;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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StringRef getPassName() const override { return SYSTEMZ_POSTREWRITE_NAME; }
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private:
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void selectLOCRMux(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LowOpcode,
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unsigned HighOpcode);
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void selectSELRMux(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LowOpcode,
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unsigned HighOpcode);
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bool expandCondMove(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool selectMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool selectMBB(MachineBasicBlock &MBB);
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};
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char SystemZPostRewrite::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(SystemZPostRewrite, "systemz-post-rewrite",
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SYSTEMZ_POSTREWRITE_NAME, false, false)
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/// Returns an instance of the Post Rewrite pass.
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FunctionPass *llvm::createSystemZPostRewritePass(SystemZTargetMachine &TM) {
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return new SystemZPostRewrite();
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}
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// MI is a load-register-on-condition pseudo instruction. Replace it with
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// LowOpcode if source and destination are both low GR32s and HighOpcode if
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// source and destination are both high GR32s. Otherwise, a branch sequence
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// is created.
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void SystemZPostRewrite::selectLOCRMux(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LowOpcode,
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unsigned HighOpcode) {
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Register DestReg = MBBI->getOperand(0).getReg();
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Register SrcReg = MBBI->getOperand(2).getReg();
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bool DestIsHigh = SystemZ::isHighReg(DestReg);
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bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
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if (!DestIsHigh && !SrcIsHigh)
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MBBI->setDesc(TII->get(LowOpcode));
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else if (DestIsHigh && SrcIsHigh)
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MBBI->setDesc(TII->get(HighOpcode));
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else
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expandCondMove(MBB, MBBI, NextMBBI);
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}
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// MI is a select pseudo instruction. Replace it with LowOpcode if source
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// and destination are all low GR32s and HighOpcode if source and destination
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// are all high GR32s. Otherwise, a branch sequence is created.
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void SystemZPostRewrite::selectSELRMux(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LowOpcode,
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unsigned HighOpcode) {
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Register DestReg = MBBI->getOperand(0).getReg();
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Register Src1Reg = MBBI->getOperand(1).getReg();
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Register Src2Reg = MBBI->getOperand(2).getReg();
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bool DestIsHigh = SystemZ::isHighReg(DestReg);
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bool Src1IsHigh = SystemZ::isHighReg(Src1Reg);
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bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
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// If sources and destination aren't all high or all low, we may be able to
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// simplify the operation by moving one of the sources to the destination
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// first. But only if this doesn't clobber the other source.
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if (DestReg != Src1Reg && DestReg != Src2Reg) {
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if (DestIsHigh != Src1IsHigh) {
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BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
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TII->get(SystemZ::COPY), DestReg)
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.addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
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MBBI->getOperand(1).setReg(DestReg);
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Src1Reg = DestReg;
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Src1IsHigh = DestIsHigh;
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} else if (DestIsHigh != Src2IsHigh) {
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BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
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TII->get(SystemZ::COPY), DestReg)
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.addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
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MBBI->getOperand(2).setReg(DestReg);
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Src2Reg = DestReg;
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Src2IsHigh = DestIsHigh;
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}
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}
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// If the destination (now) matches one source, prefer this to be first.
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if (DestReg != Src1Reg && DestReg == Src2Reg) {
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TII->commuteInstruction(*MBBI, false, 1, 2);
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std::swap(Src1Reg, Src2Reg);
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std::swap(Src1IsHigh, Src2IsHigh);
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}
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if (!DestIsHigh && !Src1IsHigh && !Src2IsHigh)
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MBBI->setDesc(TII->get(LowOpcode));
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else if (DestIsHigh && Src1IsHigh && Src2IsHigh)
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MBBI->setDesc(TII->get(HighOpcode));
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else
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// Given the simplification above, we must already have a two-operand case.
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expandCondMove(MBB, MBBI, NextMBBI);
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}
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// Replace MBBI by a branch sequence that performs a conditional move of
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// operand 2 to the destination register. Operand 1 is expected to be the
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// same register as the destination.
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bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction &MF = *MBB.getParent();
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const BasicBlock *BB = MBB.getBasicBlock();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register DestReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(2).getReg();
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unsigned CCValid = MI.getOperand(3).getImm();
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unsigned CCMask = MI.getOperand(4).getImm();
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assert(DestReg == MI.getOperand(1).getReg() &&
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"Expected destination and first source operand to be the same.");
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LivePhysRegs LiveRegs(TII->getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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for (auto I = std::prev(MBB.end()); I != MBBI; --I)
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LiveRegs.stepBackward(*I);
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// Splice MBB at MI, moving the rest of the block into RestMBB.
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MachineBasicBlock *RestMBB = MF.CreateMachineBasicBlock(BB);
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MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
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RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
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RestMBB->transferSuccessors(&MBB);
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for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
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RestMBB->addLiveIn(*I);
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// Create a new block MoveMBB to hold the move instruction.
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MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
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MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
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MoveMBB->addLiveIn(SrcReg);
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for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
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MoveMBB->addLiveIn(*I);
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// At the end of MBB, create a conditional branch to RestMBB if the
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// condition is false, otherwise fall through to MoveMBB.
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BuildMI(&MBB, DL, TII->get(SystemZ::BRC))
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.addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
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MBB.addSuccessor(RestMBB);
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MBB.addSuccessor(MoveMBB);
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// In MoveMBB, emit an instruction to move SrcReg into DestReg,
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// then fall through to RestMBB.
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BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
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.addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
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MoveMBB->addSuccessor(RestMBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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LOCRMuxJumps++;
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return true;
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}
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/// If MBBI references a pseudo instruction that should be selected here,
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/// do it and return true. Otherwise return false.
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bool SystemZPostRewrite::selectMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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// Note: If this could be done during regalloc in foldMemoryOperandImpl()
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// while also updating the LiveIntervals, there would be no need for the
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// MemFoldPseudo to begin with.
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int TargetMemOpcode = SystemZ::getTargetMemOpcode(Opcode);
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if (TargetMemOpcode != -1) {
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MI.setDesc(TII->get(TargetMemOpcode));
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MI.tieOperands(0, 1);
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Register DstReg = MI.getOperand(0).getReg();
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MachineOperand &SrcMO = MI.getOperand(1);
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if (DstReg != SrcMO.getReg()) {
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(SystemZ::COPY), DstReg)
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.addReg(SrcMO.getReg());
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SrcMO.setReg(DstReg);
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MemFoldCopies++;
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}
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return true;
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}
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switch (Opcode) {
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case SystemZ::LOCRMux:
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selectLOCRMux(MBB, MBBI, NextMBBI, SystemZ::LOCR, SystemZ::LOCFHR);
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return true;
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case SystemZ::SELRMux:
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selectSELRMux(MBB, MBBI, NextMBBI, SystemZ::SELR, SystemZ::SELFHR);
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return true;
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}
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return false;
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}
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/// Iterate over the instructions in basic block MBB and select any
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/// pseudo instructions. Return true if anything was modified.
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bool SystemZPostRewrite::selectMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= selectMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool SystemZPostRewrite::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= selectMBB(MBB);
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return Modified;
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}
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