472 lines
16 KiB
C++
472 lines
16 KiB
C++
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//===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass makes sure that all branches are in range. There are several ways
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// in which this could be done. One aggressive approach is to assume that all
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// branches are in range and successively replace those that turn out not
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// to be in range with a longer form (branch relaxation). A simple
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// implementation is to continually walk through the function relaxing
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// branches until no more changes are needed and a fixed point is reached.
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// However, in the pathological worst case, this implementation is
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// quadratic in the number of blocks; relaxing branch N can make branch N-1
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// go out of range, which in turn can make branch N-2 go out of range,
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// and so on.
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//
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// An alternative approach is to assume that all branches must be
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// converted to their long forms, then reinstate the short forms of
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// branches that, even under this pessimistic assumption, turn out to be
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// in range (branch shortening). This too can be implemented as a function
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// walk that is repeated until a fixed point is reached. In general,
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// the result of shortening is not as good as that of relaxation, and
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// shortening is also quadratic in the worst case; shortening branch N
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// can bring branch N-1 in range of the short form, which in turn can do
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// the same for branch N-2, and so on. The main advantage of shortening
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// is that each walk through the function produces valid code, so it is
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// possible to stop at any point after the first walk. The quadraticness
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// could therefore be handled with a maximum pass count, although the
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// question then becomes: what maximum count should be used?
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//
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// On SystemZ, long branches are only needed for functions bigger than 64k,
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// which are relatively rare to begin with, and the long branch sequences
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// are actually relatively cheap. It therefore doesn't seem worth spending
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// much compilation time on the problem. Instead, the approach we take is:
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//
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// (1) Work out the address that each block would have if no branches
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// need relaxing. Exit the pass early if all branches are in range
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// according to this assumption.
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//
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// (2) Work out the address that each block would have if all branches
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// need relaxing.
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//
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// (3) Walk through the block calculating the final address of each instruction
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// and relaxing those that need to be relaxed. For backward branches,
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// this check uses the final address of the target block, as calculated
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// earlier in the walk. For forward branches, this check uses the
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// address of the target block that was calculated in (2). Both checks
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// give a conservatively-correct range.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "systemz-long-branch"
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STATISTIC(LongBranches, "Number of long branches.");
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namespace {
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// Represents positional information about a basic block.
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struct MBBInfo {
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// The address that we currently assume the block has.
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uint64_t Address = 0;
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// The size of the block in bytes, excluding terminators.
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// This value never changes.
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uint64_t Size = 0;
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// The minimum alignment of the block.
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// This value never changes.
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Align Alignment;
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// The number of terminators in this block. This value never changes.
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unsigned NumTerminators = 0;
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MBBInfo() = default;
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};
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// Represents the state of a block terminator.
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struct TerminatorInfo {
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// If this terminator is a relaxable branch, this points to the branch
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// instruction, otherwise it is null.
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MachineInstr *Branch = nullptr;
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// The address that we currently assume the terminator has.
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uint64_t Address = 0;
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// The current size of the terminator in bytes.
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uint64_t Size = 0;
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// If Branch is nonnull, this is the number of the target block,
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// otherwise it is unused.
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unsigned TargetBlock = 0;
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// If Branch is nonnull, this is the length of the longest relaxed form,
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// otherwise it is zero.
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unsigned ExtraRelaxSize = 0;
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TerminatorInfo() = default;
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};
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// Used to keep track of the current position while iterating over the blocks.
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struct BlockPosition {
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// The address that we assume this position has.
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uint64_t Address = 0;
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// The number of low bits in Address that are known to be the same
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// as the runtime address.
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unsigned KnownBits;
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BlockPosition(unsigned InitialLogAlignment)
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: KnownBits(InitialLogAlignment) {}
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};
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class SystemZLongBranch : public MachineFunctionPass {
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public:
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static char ID;
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SystemZLongBranch(const SystemZTargetMachine &tm)
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: MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "SystemZ Long Branch"; }
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
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void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
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bool AssumeRelaxed);
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TerminatorInfo describeTerminator(MachineInstr &MI);
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uint64_t initMBBInfo();
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bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);
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bool mustRelaxABranch();
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void setWorstCaseAddresses();
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void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode);
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void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode);
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void relaxBranch(TerminatorInfo &Terminator);
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void relaxBranches();
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const SystemZInstrInfo *TII = nullptr;
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MachineFunction *MF = nullptr;
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SmallVector<MBBInfo, 16> MBBs;
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SmallVector<TerminatorInfo, 16> Terminators;
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};
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char SystemZLongBranch::ID = 0;
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const uint64_t MaxBackwardRange = 0x10000;
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const uint64_t MaxForwardRange = 0xfffe;
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} // end anonymous namespace
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// Position describes the state immediately before Block. Update Block
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// accordingly and move Position to the end of the block's non-terminator
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// instructions.
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void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
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MBBInfo &Block) {
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if (Log2(Block.Alignment) > Position.KnownBits) {
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// When calculating the address of Block, we need to conservatively
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// assume that Block had the worst possible misalignment.
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Position.Address +=
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(Block.Alignment.value() - (uint64_t(1) << Position.KnownBits));
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Position.KnownBits = Log2(Block.Alignment);
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}
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// Align the addresses.
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Position.Address = alignTo(Position.Address, Block.Alignment);
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// Record the block's position.
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Block.Address = Position.Address;
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// Move past the non-terminators in the block.
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Position.Address += Block.Size;
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}
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// Position describes the state immediately before Terminator.
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// Update Terminator accordingly and move Position past it.
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// Assume that Terminator will be relaxed if AssumeRelaxed.
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void SystemZLongBranch::skipTerminator(BlockPosition &Position,
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TerminatorInfo &Terminator,
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bool AssumeRelaxed) {
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Terminator.Address = Position.Address;
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Position.Address += Terminator.Size;
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if (AssumeRelaxed)
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Position.Address += Terminator.ExtraRelaxSize;
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}
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// Return a description of terminator instruction MI.
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TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) {
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TerminatorInfo Terminator;
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Terminator.Size = TII->getInstSizeInBytes(MI);
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if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
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switch (MI.getOpcode()) {
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case SystemZ::J:
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// Relaxes to JG, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::BRC:
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// Relaxes to BRCL, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::BRCT:
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case SystemZ::BRCTG:
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// Relaxes to A(G)HI and BRCL, which is 6 bytes longer.
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Terminator.ExtraRelaxSize = 6;
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break;
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case SystemZ::BRCTH:
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// Never needs to be relaxed.
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Terminator.ExtraRelaxSize = 0;
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break;
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case SystemZ::CRJ:
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case SystemZ::CLRJ:
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// Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::CGRJ:
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case SystemZ::CLGRJ:
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// Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer.
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Terminator.ExtraRelaxSize = 4;
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break;
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case SystemZ::CIJ:
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case SystemZ::CGIJ:
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// Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer.
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Terminator.ExtraRelaxSize = 4;
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break;
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case SystemZ::CLIJ:
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case SystemZ::CLGIJ:
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// Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer.
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Terminator.ExtraRelaxSize = 6;
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break;
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default:
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llvm_unreachable("Unrecognized branch instruction");
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}
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Terminator.Branch = &MI;
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Terminator.TargetBlock =
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TII->getBranchInfo(MI).getMBBTarget()->getNumber();
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}
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return Terminator;
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}
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// Fill MBBs and Terminators, setting the addresses on the assumption
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// that no branches need relaxation. Return the size of the function under
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// this assumption.
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uint64_t SystemZLongBranch::initMBBInfo() {
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MF->RenumberBlocks();
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unsigned NumBlocks = MF->size();
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MBBs.clear();
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MBBs.resize(NumBlocks);
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Terminators.clear();
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Terminators.reserve(NumBlocks);
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BlockPosition Position(Log2(MF->getAlignment()));
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for (unsigned I = 0; I < NumBlocks; ++I) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(I);
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MBBInfo &Block = MBBs[I];
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// Record the alignment, for quick access.
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Block.Alignment = MBB->getAlignment();
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// Calculate the size of the fixed part of the block.
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MachineBasicBlock::iterator MI = MBB->begin();
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MachineBasicBlock::iterator End = MBB->end();
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while (MI != End && !MI->isTerminator()) {
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Block.Size += TII->getInstSizeInBytes(*MI);
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++MI;
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}
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skipNonTerminators(Position, Block);
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// Add the terminators.
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while (MI != End) {
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if (!MI->isDebugInstr()) {
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assert(MI->isTerminator() && "Terminator followed by non-terminator");
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Terminators.push_back(describeTerminator(*MI));
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skipTerminator(Position, Terminators.back(), false);
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++Block.NumTerminators;
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}
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++MI;
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}
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}
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return Position.Address;
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}
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// Return true if, under current assumptions, Terminator would need to be
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// relaxed if it were placed at address Address.
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bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator,
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uint64_t Address) {
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if (!Terminator.Branch || Terminator.ExtraRelaxSize == 0)
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return false;
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const MBBInfo &Target = MBBs[Terminator.TargetBlock];
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if (Address >= Target.Address) {
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if (Address - Target.Address <= MaxBackwardRange)
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return false;
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} else {
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if (Target.Address - Address <= MaxForwardRange)
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return false;
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}
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return true;
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}
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// Return true if, under current assumptions, any terminator needs
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// to be relaxed.
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bool SystemZLongBranch::mustRelaxABranch() {
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for (auto &Terminator : Terminators)
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if (mustRelaxBranch(Terminator, Terminator.Address))
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return true;
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return false;
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}
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// Set the address of each block on the assumption that all branches
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// must be long.
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void SystemZLongBranch::setWorstCaseAddresses() {
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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BlockPosition Position(Log2(MF->getAlignment()));
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for (auto &Block : MBBs) {
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skipNonTerminators(Position, Block);
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for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
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skipTerminator(Position, *TI, true);
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++TI;
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}
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}
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}
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// Split BRANCH ON COUNT MI into the addition given by AddOpcode followed
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// by a BRCL on the result.
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void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI,
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unsigned AddOpcode) {
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MachineBasicBlock *MBB = MI->getParent();
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DebugLoc DL = MI->getDebugLoc();
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BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
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.add(MI->getOperand(0))
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.add(MI->getOperand(1))
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.addImm(-1);
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MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
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.addImm(SystemZ::CCMASK_ICMP)
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.addImm(SystemZ::CCMASK_CMP_NE)
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.add(MI->getOperand(2));
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// The implicit use of CC is a killing use.
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|
BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
|
||
|
|
MI->eraseFromParent();
|
||
|
|
}
|
||
|
|
|
||
|
|
// Split MI into the comparison given by CompareOpcode followed
|
||
|
|
// a BRCL on the result.
|
||
|
|
void SystemZLongBranch::splitCompareBranch(MachineInstr *MI,
|
||
|
|
unsigned CompareOpcode) {
|
||
|
|
MachineBasicBlock *MBB = MI->getParent();
|
||
|
|
DebugLoc DL = MI->getDebugLoc();
|
||
|
|
BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
|
||
|
|
.add(MI->getOperand(0))
|
||
|
|
.add(MI->getOperand(1));
|
||
|
|
MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
|
||
|
|
.addImm(SystemZ::CCMASK_ICMP)
|
||
|
|
.add(MI->getOperand(2))
|
||
|
|
.add(MI->getOperand(3));
|
||
|
|
// The implicit use of CC is a killing use.
|
||
|
|
BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
|
||
|
|
MI->eraseFromParent();
|
||
|
|
}
|
||
|
|
|
||
|
|
// Relax the branch described by Terminator.
|
||
|
|
void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
|
||
|
|
MachineInstr *Branch = Terminator.Branch;
|
||
|
|
switch (Branch->getOpcode()) {
|
||
|
|
case SystemZ::J:
|
||
|
|
Branch->setDesc(TII->get(SystemZ::JG));
|
||
|
|
break;
|
||
|
|
case SystemZ::BRC:
|
||
|
|
Branch->setDesc(TII->get(SystemZ::BRCL));
|
||
|
|
break;
|
||
|
|
case SystemZ::BRCT:
|
||
|
|
splitBranchOnCount(Branch, SystemZ::AHI);
|
||
|
|
break;
|
||
|
|
case SystemZ::BRCTG:
|
||
|
|
splitBranchOnCount(Branch, SystemZ::AGHI);
|
||
|
|
break;
|
||
|
|
case SystemZ::CRJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CR);
|
||
|
|
break;
|
||
|
|
case SystemZ::CGRJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CGR);
|
||
|
|
break;
|
||
|
|
case SystemZ::CIJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CHI);
|
||
|
|
break;
|
||
|
|
case SystemZ::CGIJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CGHI);
|
||
|
|
break;
|
||
|
|
case SystemZ::CLRJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CLR);
|
||
|
|
break;
|
||
|
|
case SystemZ::CLGRJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CLGR);
|
||
|
|
break;
|
||
|
|
case SystemZ::CLIJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CLFI);
|
||
|
|
break;
|
||
|
|
case SystemZ::CLGIJ:
|
||
|
|
splitCompareBranch(Branch, SystemZ::CLGFI);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
llvm_unreachable("Unrecognized branch");
|
||
|
|
}
|
||
|
|
|
||
|
|
Terminator.Size += Terminator.ExtraRelaxSize;
|
||
|
|
Terminator.ExtraRelaxSize = 0;
|
||
|
|
Terminator.Branch = nullptr;
|
||
|
|
|
||
|
|
++LongBranches;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Run a shortening pass and relax any branches that need to be relaxed.
|
||
|
|
void SystemZLongBranch::relaxBranches() {
|
||
|
|
SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
|
||
|
|
BlockPosition Position(Log2(MF->getAlignment()));
|
||
|
|
for (auto &Block : MBBs) {
|
||
|
|
skipNonTerminators(Position, Block);
|
||
|
|
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
|
||
|
|
assert(Position.Address <= TI->Address &&
|
||
|
|
"Addresses shouldn't go forwards");
|
||
|
|
if (mustRelaxBranch(*TI, Position.Address))
|
||
|
|
relaxBranch(*TI);
|
||
|
|
skipTerminator(Position, *TI, false);
|
||
|
|
++TI;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) {
|
||
|
|
TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
|
||
|
|
MF = &F;
|
||
|
|
uint64_t Size = initMBBInfo();
|
||
|
|
if (Size <= MaxForwardRange || !mustRelaxABranch())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
setWorstCaseAddresses();
|
||
|
|
relaxBranches();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) {
|
||
|
|
return new SystemZLongBranch(TM);
|
||
|
|
}
|