425 lines
14 KiB
C++
425 lines
14 KiB
C++
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//===-- LanaiMemAluCombiner.cpp - Pass to combine memory & ALU operations -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Simple pass to combine memory and ALU operations
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//
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// The Lanai ISA supports instructions where a load/store modifies the base
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// register used in the load/store operation. This pass finds suitable
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// load/store and ALU instructions and combines them into one instruction.
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//
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// For example,
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// ld [ %r6 -- ], %r12
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// is a supported instruction that is not currently generated by the instruction
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// selection pass of this backend. This pass generates these instructions by
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// merging
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// add %r6, -4, %r6
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// followed by
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// ld [ %r6 ], %r12
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// in the same machine basic block into one machine instruction.
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//===----------------------------------------------------------------------===//
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#include "LanaiAluCode.h"
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#include "LanaiTargetMachine.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define GET_INSTRMAP_INFO
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#include "LanaiGenInstrInfo.inc"
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#define DEBUG_TYPE "lanai-mem-alu-combiner"
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STATISTIC(NumLdStAluCombined, "Number of memory and ALU instructions combined");
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static llvm::cl::opt<bool> DisableMemAluCombiner(
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"disable-lanai-mem-alu-combiner", llvm::cl::init(false),
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llvm::cl::desc("Do not combine ALU and memory operators"),
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llvm::cl::Hidden);
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namespace llvm {
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void initializeLanaiMemAluCombinerPass(PassRegistry &);
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} // namespace llvm
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namespace {
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typedef MachineBasicBlock::iterator MbbIterator;
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typedef MachineFunction::iterator MfIterator;
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class LanaiMemAluCombiner : public MachineFunctionPass {
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public:
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static char ID;
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explicit LanaiMemAluCombiner() : MachineFunctionPass(ID) {
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initializeLanaiMemAluCombinerPass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override {
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return "Lanai load / store optimization pass";
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}
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB,
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const MbbIterator &MemInstr,
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bool Decrement);
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void insertMergedInstruction(MachineBasicBlock *BB,
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const MbbIterator &MemInstr,
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const MbbIterator &AluInstr, bool Before);
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bool combineMemAluInBasicBlock(MachineBasicBlock *BB);
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// Target machine description which we query for register names, data
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// layout, etc.
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const TargetInstrInfo *TII;
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};
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} // namespace
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char LanaiMemAluCombiner::ID = 0;
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INITIALIZE_PASS(LanaiMemAluCombiner, DEBUG_TYPE,
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"Lanai memory ALU combiner pass", false, false)
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namespace {
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bool isSpls(uint16_t Opcode) { return Lanai::splsIdempotent(Opcode) == Opcode; }
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// Determine the opcode for the merged instruction created by considering the
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// old memory operation's opcode and whether the merged opcode will have an
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// immediate offset.
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unsigned mergedOpcode(unsigned OldOpcode, bool ImmediateOffset) {
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switch (OldOpcode) {
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case Lanai::LDW_RI:
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case Lanai::LDW_RR:
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if (ImmediateOffset)
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return Lanai::LDW_RI;
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return Lanai::LDW_RR;
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case Lanai::LDHs_RI:
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case Lanai::LDHs_RR:
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if (ImmediateOffset)
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return Lanai::LDHs_RI;
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return Lanai::LDHs_RR;
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case Lanai::LDHz_RI:
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case Lanai::LDHz_RR:
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if (ImmediateOffset)
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return Lanai::LDHz_RI;
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return Lanai::LDHz_RR;
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case Lanai::LDBs_RI:
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case Lanai::LDBs_RR:
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if (ImmediateOffset)
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return Lanai::LDBs_RI;
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return Lanai::LDBs_RR;
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case Lanai::LDBz_RI:
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case Lanai::LDBz_RR:
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if (ImmediateOffset)
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return Lanai::LDBz_RI;
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return Lanai::LDBz_RR;
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case Lanai::SW_RI:
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case Lanai::SW_RR:
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if (ImmediateOffset)
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return Lanai::SW_RI;
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return Lanai::SW_RR;
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case Lanai::STB_RI:
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case Lanai::STB_RR:
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if (ImmediateOffset)
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return Lanai::STB_RI;
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return Lanai::STB_RR;
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case Lanai::STH_RI:
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case Lanai::STH_RR:
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if (ImmediateOffset)
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return Lanai::STH_RI;
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return Lanai::STH_RR;
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default:
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return 0;
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}
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}
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// Check if the machine instruction has non-volatile memory operands of the type
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// supported for combining with ALU instructions.
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bool isNonVolatileMemoryOp(const MachineInstr &MI) {
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if (!MI.hasOneMemOperand())
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return false;
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// Determine if the machine instruction is a supported memory operation by
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// testing if the computed merge opcode is a valid memory operation opcode.
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if (mergedOpcode(MI.getOpcode(), false) == 0)
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return false;
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const MachineMemOperand *MemOperand = *MI.memoperands_begin();
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// Don't move volatile memory accesses
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// TODO: unclear if we need to be as conservative about atomics
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if (MemOperand->isVolatile() || MemOperand->isAtomic())
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return false;
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return true;
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}
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// Test to see if two machine operands are of the same type. This test is less
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// strict than the MachineOperand::isIdenticalTo function.
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bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
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if (Op1.getType() != Op2.getType())
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return false;
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switch (Op1.getType()) {
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case MachineOperand::MO_Register:
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return Op1.getReg() == Op2.getReg();
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case MachineOperand::MO_Immediate:
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return Op1.getImm() == Op2.getImm();
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default:
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return false;
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}
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}
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bool isZeroOperand(const MachineOperand &Op) {
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return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
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(Op.isImm() && Op.getImm() == 0));
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}
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// Determines whether a register is used by an instruction.
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bool InstrUsesReg(const MbbIterator &Instr, const MachineOperand *Reg) {
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for (MachineInstr::const_mop_iterator Mop = Instr->operands_begin();
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Mop != Instr->operands_end(); ++Mop) {
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if (isSameOperand(*Mop, *Reg))
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return true;
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}
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return false;
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}
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// Converts between machine opcode and AluCode.
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// Flag using/modifying ALU operations should not be considered for merging and
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// are omitted from this list.
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LPAC::AluCode mergedAluCode(unsigned AluOpcode) {
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switch (AluOpcode) {
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case Lanai::ADD_I_LO:
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case Lanai::ADD_R:
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return LPAC::ADD;
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case Lanai::SUB_I_LO:
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case Lanai::SUB_R:
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return LPAC::SUB;
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case Lanai::AND_I_LO:
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case Lanai::AND_R:
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return LPAC::AND;
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case Lanai::OR_I_LO:
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case Lanai::OR_R:
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return LPAC::OR;
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case Lanai::XOR_I_LO:
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case Lanai::XOR_R:
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return LPAC::XOR;
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case Lanai::SHL_R:
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return LPAC::SHL;
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case Lanai::SRL_R:
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return LPAC::SRL;
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case Lanai::SRA_R:
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return LPAC::SRA;
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case Lanai::SA_I:
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case Lanai::SL_I:
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default:
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return LPAC::UNKNOWN;
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}
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}
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// Insert a new combined memory and ALU operation instruction.
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//
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// This function builds a new machine instruction using the MachineInstrBuilder
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// class and inserts it before the memory instruction.
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void LanaiMemAluCombiner::insertMergedInstruction(MachineBasicBlock *BB,
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const MbbIterator &MemInstr,
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const MbbIterator &AluInstr,
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bool Before) {
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// Insert new combined load/store + alu operation
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MachineOperand Dest = MemInstr->getOperand(0);
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MachineOperand Base = MemInstr->getOperand(1);
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MachineOperand MemOffset = MemInstr->getOperand(2);
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MachineOperand AluOffset = AluInstr->getOperand(2);
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// Abort if ALU offset is not a register or immediate
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assert((AluOffset.isReg() || AluOffset.isImm()) &&
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"Unsupported operand type in merge");
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// Determined merged instructions opcode and ALU code
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LPAC::AluCode AluOpcode = mergedAluCode(AluInstr->getOpcode());
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unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm());
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assert(AluOpcode != LPAC::UNKNOWN && "Unknown ALU code in merging");
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assert(NewOpc != 0 && "Unknown merged node opcode");
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// Build and insert new machine instruction
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MachineInstrBuilder InstrBuilder =
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BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
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InstrBuilder.addReg(Dest.getReg(), getDefRegState(true));
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InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
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// Add offset to machine instruction
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if (AluOffset.isReg())
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InstrBuilder.addReg(AluOffset.getReg());
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else if (AluOffset.isImm())
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InstrBuilder.addImm(AluOffset.getImm());
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else
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llvm_unreachable("Unsupported ld/st ALU merge.");
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// Create a pre-op if the ALU operation preceded the memory operation or the
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// MemOffset is non-zero (i.e. the memory value should be adjusted before
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// accessing it), else create a post-op.
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if (Before || !isZeroOperand(MemOffset))
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InstrBuilder.addImm(LPAC::makePreOp(AluOpcode));
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else
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InstrBuilder.addImm(LPAC::makePostOp(AluOpcode));
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// Transfer memory operands.
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InstrBuilder.setMemRefs(MemInstr->memoperands());
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}
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// Function determines if ALU operation (in alu_iter) can be combined with
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// a load/store with base and offset.
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bool isSuitableAluInstr(bool IsSpls, const MbbIterator &AluIter,
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const MachineOperand &Base,
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const MachineOperand &Offset) {
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// ALU operations have 3 operands
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if (AluIter->getNumOperands() != 3)
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return false;
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MachineOperand &Dest = AluIter->getOperand(0);
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MachineOperand &Op1 = AluIter->getOperand(1);
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MachineOperand &Op2 = AluIter->getOperand(2);
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// Only match instructions using the base register as destination and with the
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// base and first operand equal
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if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1))
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return false;
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if (Op2.isImm()) {
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// It is not a match if the 2nd operand in the ALU operation is an
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// immediate but the ALU operation is not an addition.
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if (AluIter->getOpcode() != Lanai::ADD_I_LO)
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return false;
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if (Offset.isReg() && Offset.getReg() == Lanai::R0)
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return true;
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if (Offset.isImm() &&
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((Offset.getImm() == 0 &&
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// Check that the Op2 would fit in the immediate field of the
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// memory operation.
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((IsSpls && isInt<10>(Op2.getImm())) ||
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(!IsSpls && isInt<16>(Op2.getImm())))) ||
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Offset.getImm() == Op2.getImm()))
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return true;
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} else if (Op2.isReg()) {
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// The Offset and 2nd operand are both registers and equal
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if (Offset.isReg() && Op2.getReg() == Offset.getReg())
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return true;
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} else
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// Only consider operations with register or immediate values
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return false;
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return false;
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}
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MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr(
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MachineBasicBlock *BB, const MbbIterator &MemInstr, const bool Decrement) {
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MachineOperand *Base = &MemInstr->getOperand(1);
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MachineOperand *Offset = &MemInstr->getOperand(2);
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bool IsSpls = isSpls(MemInstr->getOpcode());
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MbbIterator First = MemInstr;
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MbbIterator Last = Decrement ? BB->begin() : BB->end();
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while (First != Last) {
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Decrement ? --First : ++First;
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if (First == Last)
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break;
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// Skip over debug instructions
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if (First->isDebugInstr())
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continue;
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if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) {
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return First;
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}
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// Usage of the base or offset register is not a form suitable for merging.
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if (First != Last) {
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if (InstrUsesReg(First, Base))
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break;
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if (Offset->isReg() && InstrUsesReg(First, Offset))
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break;
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}
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}
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return MemInstr;
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}
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bool LanaiMemAluCombiner::combineMemAluInBasicBlock(MachineBasicBlock *BB) {
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|
bool Modified = false;
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||
|
|
|
||
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|
MbbIterator MBBIter = BB->begin(), End = BB->end();
|
||
|
|
while (MBBIter != End) {
|
||
|
|
bool IsMemOp = isNonVolatileMemoryOp(*MBBIter);
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||
|
|
|
||
|
|
if (IsMemOp) {
|
||
|
|
MachineOperand AluOperand = MBBIter->getOperand(3);
|
||
|
|
unsigned int DestReg = MBBIter->getOperand(0).getReg(),
|
||
|
|
BaseReg = MBBIter->getOperand(1).getReg();
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||
|
|
assert(AluOperand.isImm() && "Unexpected memory operator type");
|
||
|
|
LPAC::AluCode AluOpcode = static_cast<LPAC::AluCode>(AluOperand.getImm());
|
||
|
|
|
||
|
|
// Skip memory operations that already modify the base register or if
|
||
|
|
// the destination and base register are the same
|
||
|
|
if (!LPAC::modifiesOp(AluOpcode) && DestReg != BaseReg) {
|
||
|
|
for (int Inc = 0; Inc <= 1; ++Inc) {
|
||
|
|
MbbIterator AluIter =
|
||
|
|
findClosestSuitableAluInstr(BB, MBBIter, Inc == 0);
|
||
|
|
if (AluIter != MBBIter) {
|
||
|
|
insertMergedInstruction(BB, MBBIter, AluIter, Inc == 0);
|
||
|
|
|
||
|
|
++NumLdStAluCombined;
|
||
|
|
Modified = true;
|
||
|
|
|
||
|
|
// Erase the matching ALU instruction
|
||
|
|
BB->erase(AluIter);
|
||
|
|
// Erase old load/store instruction
|
||
|
|
BB->erase(MBBIter++);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (MBBIter == End)
|
||
|
|
break;
|
||
|
|
++MBBIter;
|
||
|
|
}
|
||
|
|
|
||
|
|
return Modified;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Driver function that iterates over the machine basic building blocks of a
|
||
|
|
// machine function
|
||
|
|
bool LanaiMemAluCombiner::runOnMachineFunction(MachineFunction &MF) {
|
||
|
|
if (DisableMemAluCombiner)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
TII = MF.getSubtarget<LanaiSubtarget>().getInstrInfo();
|
||
|
|
bool Modified = false;
|
||
|
|
for (MfIterator MFI = MF.begin(); MFI != MF.end(); ++MFI) {
|
||
|
|
Modified |= combineMemAluInBasicBlock(&*MFI);
|
||
|
|
}
|
||
|
|
return Modified;
|
||
|
|
}
|
||
|
|
} // namespace
|
||
|
|
|
||
|
|
FunctionPass *llvm::createLanaiMemAluCombinerPass() {
|
||
|
|
return new LanaiMemAluCombiner();
|
||
|
|
}
|