326 lines
12 KiB
TableGen
326 lines
12 KiB
TableGen
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//=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
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// below is to define a generic SchedWriteRes for every combination of
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// latency and microOps. The naming conventions is to use a prefix, one field
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// for latency, and one or more microOp count/type designators.
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// Prefix: A57Write
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// Latency: #cyc
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// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
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//
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// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
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// 11 micro-ops to be issued as follows: one to I pipe, six to S pipes and
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// four to V pipes.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Define Generic 1 micro-op types
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def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
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def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
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def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
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def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
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def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
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let ResourceCycles = [17]; }
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def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
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let ResourceCycles = [18]; }
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def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
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let ResourceCycles = [19]; }
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def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
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let ResourceCycles = [20]; }
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def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
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def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1;
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let ResourceCycles = [1]; }
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def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2;
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let ResourceCycles = [1]; }
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def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
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def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
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def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
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def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
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def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2;
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let ResourceCycles = [1]; }
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def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
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let ResourceCycles = [32]; }
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def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
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let ResourceCycles = [32]; }
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def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
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let ResourceCycles = [35]; }
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def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
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def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
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def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
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def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
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// A57Write_3cyc_1L - A57Write_20cyc_1L
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foreach Lat = 3-20 in {
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def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
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let Latency = Lat;
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}
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}
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// A57Write_4cyc_1S - A57Write_16cyc_1S
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foreach Lat = 4-16 in {
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def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
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let Latency = Lat;
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}
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}
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def A57Write_4cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 4; }
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def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
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def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; }
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def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; }
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def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; }
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def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; }
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def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; }
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def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
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def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
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def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
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//===----------------------------------------------------------------------===//
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// Define Generic 2 micro-op types
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def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 64;
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let NumMicroOps = 2;
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let ResourceCycles = [32, 32];
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}
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def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
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A57UnitL]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_1V_1X : SchedWriteRes<[A57UnitV,
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A57UnitX]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
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A57UnitX]> {
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let Latency = 7;
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let NumMicroOps = 2;
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}
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def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
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A57UnitV]> {
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let Latency = 8;
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let NumMicroOps = 2;
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}
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def A57Write_9cyc_1L_1V : SchedWriteRes<[A57UnitL,
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A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 2;
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}
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def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 9;
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let NumMicroOps = 2;
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}
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def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 8;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
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A57UnitL]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_1I_1M : SchedWriteRes<[A57UnitI,
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A57UnitM]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 5;
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let NumMicroOps = 2;
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}
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def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
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A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 2;
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}
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def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
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A57UnitS]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1S_1I : SchedWriteRes<[A57UnitS,
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A57UnitI]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_1S_1I : SchedWriteRes<[A57UnitS,
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A57UnitI]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_1S_1I : SchedWriteRes<[A57UnitS,
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A57UnitI]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_1cyc_1S_1M : SchedWriteRes<[A57UnitS,
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A57UnitM]> {
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let Latency = 1;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_1B_1I : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_6cyc_1B_1L : SchedWriteRes<[A57UnitB,
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A57UnitI]> {
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let Latency = 6;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_1I_1M : SchedWriteRes<[A57UnitI,
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A57UnitM]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 36;
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let NumMicroOps = 2;
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let ResourceCycles = [18, 18];
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}
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def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
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A57UnitM]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_4cyc_1I_1M : SchedWriteRes<[A57UnitI,
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A57UnitM]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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// A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I
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foreach Lat = 3-20 in {
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def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
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let Latency = Lat; let NumMicroOps = 2;
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}
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}
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def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
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A57UnitS]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def A57Write_4cyc_1S_1V : SchedWriteRes<[A57UnitS,
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A57UnitV]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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// A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I
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foreach Lat = 4-16 in {
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def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {
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let Latency = Lat; let NumMicroOps = 2;
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}
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}
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def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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//===----------------------------------------------------------------------===//
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// Define Generic 3 micro-op types
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def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
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let Latency = 10;
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let NumMicroOps = 3;
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}
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def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
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A57UnitS, A57UnitS]> {
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let Latency = 2;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
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A57UnitS,
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A57UnitV]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_3cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
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A57UnitV,
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A57UnitI]> {
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let Latency = 3;
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let NumMicroOps = 3;
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}
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def A57Write_4cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
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A57UnitV,
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A57UnitI]> {
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let Latency = 4;
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let NumMicroOps = 3;
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}
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def A57Write_4cyc_1I_1L_1M : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {
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let Latency = 4;
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let NumMicroOps = 3;
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}
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def A57Write_8cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,
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A57UnitV,
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A57UnitI]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def A57Write_9cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,
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A57UnitV,
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|
|
A57UnitI]> {
|
||
|
|
let Latency = 9;
|
||
|
|
let NumMicroOps = 3;
|
||
|
|
}
|