364 lines
9.7 KiB
C++
364 lines
9.7 KiB
C++
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//===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUAsmUtils.h"
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#include "SIDefines.h"
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#include "llvm/ADT/StringRef.h"
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namespace llvm {
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namespace AMDGPU {
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namespace SendMsg {
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// This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h.
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const char* const IdSymbolic[] = {
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nullptr,
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"MSG_INTERRUPT",
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"MSG_GS",
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"MSG_GS_DONE",
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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"MSG_GS_ALLOC_REQ",
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"MSG_GET_DOORBELL",
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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"MSG_SYSMSG"
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};
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// These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h.
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const char* const OpSysSymbolic[] = {
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nullptr,
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"SYSMSG_OP_ECC_ERR_INTERRUPT",
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"SYSMSG_OP_REG_RD",
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"SYSMSG_OP_HOST_TRAP_ACK",
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"SYSMSG_OP_TTRACE_PC"
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};
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const char* const OpGsSymbolic[] = {
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"GS_OP_NOP",
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"GS_OP_CUT",
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"GS_OP_EMIT",
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"GS_OP_EMIT_CUT"
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};
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} // namespace SendMsg
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namespace Hwreg {
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// This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h.
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const char* const IdSymbolic[] = {
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nullptr,
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"HW_REG_MODE",
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"HW_REG_STATUS",
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"HW_REG_TRAPSTS",
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"HW_REG_HW_ID",
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"HW_REG_GPR_ALLOC",
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"HW_REG_LDS_ALLOC",
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"HW_REG_IB_STS",
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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nullptr,
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"HW_REG_SH_MEM_BASES",
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"HW_REG_TBA_LO",
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"HW_REG_TBA_HI",
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"HW_REG_TMA_LO",
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"HW_REG_TMA_HI",
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"HW_REG_FLAT_SCR_LO",
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"HW_REG_FLAT_SCR_HI",
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"HW_REG_XNACK_MASK",
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nullptr, // HW_ID1, no predictable values
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nullptr, // HW_ID2, no predictable values
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"HW_REG_POPS_PACKER",
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nullptr,
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nullptr,
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nullptr,
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"HW_REG_SHADER_CYCLES"
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};
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} // namespace Hwreg
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namespace MTBUFFormat {
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StringLiteral const DfmtSymbolic[] = {
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"BUF_DATA_FORMAT_INVALID",
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"BUF_DATA_FORMAT_8",
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"BUF_DATA_FORMAT_16",
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"BUF_DATA_FORMAT_8_8",
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"BUF_DATA_FORMAT_32",
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"BUF_DATA_FORMAT_16_16",
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"BUF_DATA_FORMAT_10_11_11",
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"BUF_DATA_FORMAT_11_11_10",
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"BUF_DATA_FORMAT_10_10_10_2",
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"BUF_DATA_FORMAT_2_10_10_10",
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"BUF_DATA_FORMAT_8_8_8_8",
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"BUF_DATA_FORMAT_32_32",
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"BUF_DATA_FORMAT_16_16_16_16",
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"BUF_DATA_FORMAT_32_32_32",
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"BUF_DATA_FORMAT_32_32_32_32",
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"BUF_DATA_FORMAT_RESERVED_15"
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};
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StringLiteral const NfmtSymbolicGFX10[] = {
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"BUF_NUM_FORMAT_UNORM",
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"BUF_NUM_FORMAT_SNORM",
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"BUF_NUM_FORMAT_USCALED",
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"BUF_NUM_FORMAT_SSCALED",
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"BUF_NUM_FORMAT_UINT",
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"BUF_NUM_FORMAT_SINT",
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"",
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"BUF_NUM_FORMAT_FLOAT"
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};
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StringLiteral const NfmtSymbolicSICI[] = {
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"BUF_NUM_FORMAT_UNORM",
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"BUF_NUM_FORMAT_SNORM",
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"BUF_NUM_FORMAT_USCALED",
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"BUF_NUM_FORMAT_SSCALED",
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"BUF_NUM_FORMAT_UINT",
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"BUF_NUM_FORMAT_SINT",
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"BUF_NUM_FORMAT_SNORM_OGL",
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"BUF_NUM_FORMAT_FLOAT"
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};
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StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9
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"BUF_NUM_FORMAT_UNORM",
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"BUF_NUM_FORMAT_SNORM",
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"BUF_NUM_FORMAT_USCALED",
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"BUF_NUM_FORMAT_SSCALED",
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"BUF_NUM_FORMAT_UINT",
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"BUF_NUM_FORMAT_SINT",
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"BUF_NUM_FORMAT_RESERVED_6",
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"BUF_NUM_FORMAT_FLOAT"
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};
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StringLiteral const UfmtSymbolic[] = {
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"BUF_FMT_INVALID",
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"BUF_FMT_8_UNORM",
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"BUF_FMT_8_SNORM",
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"BUF_FMT_8_USCALED",
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"BUF_FMT_8_SSCALED",
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"BUF_FMT_8_UINT",
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"BUF_FMT_8_SINT",
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"BUF_FMT_16_UNORM",
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"BUF_FMT_16_SNORM",
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"BUF_FMT_16_USCALED",
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"BUF_FMT_16_SSCALED",
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"BUF_FMT_16_UINT",
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"BUF_FMT_16_SINT",
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"BUF_FMT_16_FLOAT",
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"BUF_FMT_8_8_UNORM",
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"BUF_FMT_8_8_SNORM",
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"BUF_FMT_8_8_USCALED",
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"BUF_FMT_8_8_SSCALED",
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"BUF_FMT_8_8_UINT",
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"BUF_FMT_8_8_SINT",
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"BUF_FMT_32_UINT",
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"BUF_FMT_32_SINT",
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"BUF_FMT_32_FLOAT",
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"BUF_FMT_16_16_UNORM",
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"BUF_FMT_16_16_SNORM",
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"BUF_FMT_16_16_USCALED",
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"BUF_FMT_16_16_SSCALED",
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"BUF_FMT_16_16_UINT",
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"BUF_FMT_16_16_SINT",
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"BUF_FMT_16_16_FLOAT",
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"BUF_FMT_10_11_11_UNORM",
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"BUF_FMT_10_11_11_SNORM",
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"BUF_FMT_10_11_11_USCALED",
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"BUF_FMT_10_11_11_SSCALED",
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"BUF_FMT_10_11_11_UINT",
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"BUF_FMT_10_11_11_SINT",
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"BUF_FMT_10_11_11_FLOAT",
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"BUF_FMT_11_11_10_UNORM",
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"BUF_FMT_11_11_10_SNORM",
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"BUF_FMT_11_11_10_USCALED",
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"BUF_FMT_11_11_10_SSCALED",
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"BUF_FMT_11_11_10_UINT",
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"BUF_FMT_11_11_10_SINT",
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"BUF_FMT_11_11_10_FLOAT",
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"BUF_FMT_10_10_10_2_UNORM",
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"BUF_FMT_10_10_10_2_SNORM",
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"BUF_FMT_10_10_10_2_USCALED",
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"BUF_FMT_10_10_10_2_SSCALED",
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"BUF_FMT_10_10_10_2_UINT",
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"BUF_FMT_10_10_10_2_SINT",
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"BUF_FMT_2_10_10_10_UNORM",
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"BUF_FMT_2_10_10_10_SNORM",
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"BUF_FMT_2_10_10_10_USCALED",
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"BUF_FMT_2_10_10_10_SSCALED",
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"BUF_FMT_2_10_10_10_UINT",
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"BUF_FMT_2_10_10_10_SINT",
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"BUF_FMT_8_8_8_8_UNORM",
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"BUF_FMT_8_8_8_8_SNORM",
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"BUF_FMT_8_8_8_8_USCALED",
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"BUF_FMT_8_8_8_8_SSCALED",
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"BUF_FMT_8_8_8_8_UINT",
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"BUF_FMT_8_8_8_8_SINT",
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"BUF_FMT_32_32_UINT",
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"BUF_FMT_32_32_SINT",
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"BUF_FMT_32_32_FLOAT",
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"BUF_FMT_16_16_16_16_UNORM",
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"BUF_FMT_16_16_16_16_SNORM",
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"BUF_FMT_16_16_16_16_USCALED",
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"BUF_FMT_16_16_16_16_SSCALED",
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"BUF_FMT_16_16_16_16_UINT",
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"BUF_FMT_16_16_16_16_SINT",
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"BUF_FMT_16_16_16_16_FLOAT",
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"BUF_FMT_32_32_32_UINT",
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"BUF_FMT_32_32_32_SINT",
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"BUF_FMT_32_32_32_FLOAT",
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"BUF_FMT_32_32_32_32_UINT",
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"BUF_FMT_32_32_32_32_SINT",
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"BUF_FMT_32_32_32_32_FLOAT"
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};
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unsigned const DfmtNfmt2UFmt[] = {
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DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_8 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_8 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_8 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_8 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_8 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_16 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_16 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_16 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_16 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_16 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_32 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_32 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT),
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DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT),
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DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
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DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT),
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DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT),
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DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT),
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DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
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DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT),
|
||
|
|
DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT),
|
||
|
|
DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
|
||
|
|
|
||
|
|
DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
|
||
|
|
DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
|
||
|
|
DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
|
||
|
|
DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
|
||
|
|
DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
|
||
|
|
DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT)
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace MTBUFFormat
|
||
|
|
|
||
|
|
namespace Swizzle {
|
||
|
|
|
||
|
|
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
|
||
|
|
const char* const IdSymbolic[] = {
|
||
|
|
"QUAD_PERM",
|
||
|
|
"BITMASK_PERM",
|
||
|
|
"SWAP",
|
||
|
|
"REVERSE",
|
||
|
|
"BROADCAST",
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace Swizzle
|
||
|
|
|
||
|
|
namespace VGPRIndexMode {
|
||
|
|
|
||
|
|
// This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h.
|
||
|
|
const char* const IdSymbolic[] = {
|
||
|
|
"SRC0",
|
||
|
|
"SRC1",
|
||
|
|
"SRC2",
|
||
|
|
"DST",
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace VGPRIndexMode
|
||
|
|
|
||
|
|
} // namespace AMDGPU
|
||
|
|
} // namespace llvm
|