322 lines
14 KiB
C++
322 lines
14 KiB
C++
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//===-- SchedClassResolution.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SchedClassResolution.h"
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#include "BenchmarkResult.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/FormatVariadic.h"
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#include <limits>
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#include <unordered_set>
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#include <vector>
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namespace llvm {
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namespace exegesis {
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// Return the non-redundant list of WriteProcRes used by the given sched class.
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// The scheduling model for LLVM is such that each instruction has a certain
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// number of uops which consume resources which are described by WriteProcRes
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// entries. Each entry describe how many cycles are spent on a specific ProcRes
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// kind.
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// For example, an instruction might have 3 uOps, one dispatching on P0
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// (ProcResIdx=1) and two on P06 (ProcResIdx = 7).
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// Note that LLVM additionally denormalizes resource consumption to include
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// usage of super resources by subresources. So in practice if there exists a
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// P016 (ProcResIdx=10), then the cycles consumed by P0 are also consumed by
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// P06 (ProcResIdx = 7) and P016 (ProcResIdx = 10), and the resources consumed
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// by P06 are also consumed by P016. In the figure below, parenthesized cycles
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// denote implied usage of superresources by subresources:
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// P0 P06 P016
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// uOp1 1 (1) (1)
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// uOp2 1 (1)
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// uOp3 1 (1)
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// =============================
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// 1 3 3
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// Eventually we end up with three entries for the WriteProcRes of the
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// instruction:
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// {ProcResIdx=1, Cycles=1} // P0
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// {ProcResIdx=7, Cycles=3} // P06
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// {ProcResIdx=10, Cycles=3} // P016
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//
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// Note that in this case, P016 does not contribute any cycles, so it would
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// be removed by this function.
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// FIXME: Move this to MCSubtargetInfo and use it in llvm-mca.
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static SmallVector<MCWriteProcResEntry, 8>
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getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
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const MCSubtargetInfo &STI) {
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SmallVector<MCWriteProcResEntry, 8> Result;
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const auto &SM = STI.getSchedModel();
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const unsigned NumProcRes = SM.getNumProcResourceKinds();
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// This assumes that the ProcResDescs are sorted in topological order, which
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// is guaranteed by the tablegen backend.
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SmallVector<float, 32> ProcResUnitUsage(NumProcRes);
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for (const auto *WPR = STI.getWriteProcResBegin(&SCDesc),
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*const WPREnd = STI.getWriteProcResEnd(&SCDesc);
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WPR != WPREnd; ++WPR) {
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const MCProcResourceDesc *const ProcResDesc =
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SM.getProcResource(WPR->ProcResourceIdx);
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if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
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// This is a ProcResUnit.
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Result.push_back({WPR->ProcResourceIdx, WPR->Cycles});
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ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles;
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} else {
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// This is a ProcResGroup. First see if it contributes any cycles or if
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// it has cycles just from subunits.
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float RemainingCycles = WPR->Cycles;
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for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
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SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
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++SubResIdx) {
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RemainingCycles -= ProcResUnitUsage[*SubResIdx];
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}
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if (RemainingCycles < 0.01f) {
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// The ProcResGroup contributes no cycles of its own.
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continue;
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}
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// The ProcResGroup contributes `RemainingCycles` cycles of its own.
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Result.push_back({WPR->ProcResourceIdx,
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static_cast<uint16_t>(std::round(RemainingCycles))});
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// Spread the remaining cycles over all subunits.
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for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
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SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
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++SubResIdx) {
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ProcResUnitUsage[*SubResIdx] += RemainingCycles / ProcResDesc->NumUnits;
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}
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}
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}
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return Result;
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}
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// Distributes a pressure budget as evenly as possible on the provided subunits
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// given the already existing port pressure distribution.
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//
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// The algorithm is as follows: while there is remaining pressure to
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// distribute, find the subunits with minimal pressure, and distribute
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// remaining pressure equally up to the pressure of the unit with
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// second-to-minimal pressure.
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// For example, let's assume we want to distribute 2*P1256
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// (Subunits = [P1,P2,P5,P6]), and the starting DensePressure is:
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// DensePressure = P0 P1 P2 P3 P4 P5 P6 P7
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// 0.1 0.3 0.2 0.0 0.0 0.5 0.5 0.5
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// RemainingPressure = 2.0
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// We sort the subunits by pressure:
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// Subunits = [(P2,p=0.2), (P1,p=0.3), (P5,p=0.5), (P6, p=0.5)]
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// We'll first start by the subunits with minimal pressure, which are at
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// the beginning of the sorted array. In this example there is one (P2).
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// The subunit with second-to-minimal pressure is the next one in the
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// array (P1). So we distribute 0.1 pressure to P2, and remove 0.1 cycles
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// from the budget.
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// Subunits = [(P2,p=0.3), (P1,p=0.3), (P5,p=0.5), (P5,p=0.5)]
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// RemainingPressure = 1.9
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// We repeat this process: distribute 0.2 pressure on each of the minimal
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// P2 and P1, decrease budget by 2*0.2:
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// Subunits = [(P2,p=0.5), (P1,p=0.5), (P5,p=0.5), (P5,p=0.5)]
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// RemainingPressure = 1.5
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// There are no second-to-minimal subunits so we just share the remaining
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// budget (1.5 cycles) equally:
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// Subunits = [(P2,p=0.875), (P1,p=0.875), (P5,p=0.875), (P5,p=0.875)]
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// RemainingPressure = 0.0
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// We stop as there is no remaining budget to distribute.
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static void distributePressure(float RemainingPressure,
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SmallVector<uint16_t, 32> Subunits,
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SmallVector<float, 32> &DensePressure) {
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// Find the number of subunits with minimal pressure (they are at the
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// front).
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sort(Subunits, [&DensePressure](const uint16_t A, const uint16_t B) {
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return DensePressure[A] < DensePressure[B];
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});
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const auto getPressureForSubunit = [&DensePressure,
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&Subunits](size_t I) -> float & {
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return DensePressure[Subunits[I]];
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};
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size_t NumMinimalSU = 1;
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while (NumMinimalSU < Subunits.size() &&
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getPressureForSubunit(NumMinimalSU) == getPressureForSubunit(0)) {
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++NumMinimalSU;
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}
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while (RemainingPressure > 0.0f) {
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if (NumMinimalSU == Subunits.size()) {
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// All units are minimal, just distribute evenly and be done.
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for (size_t I = 0; I < NumMinimalSU; ++I) {
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getPressureForSubunit(I) += RemainingPressure / NumMinimalSU;
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}
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return;
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}
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// Distribute the remaining pressure equally.
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const float MinimalPressure = getPressureForSubunit(NumMinimalSU - 1);
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const float SecondToMinimalPressure = getPressureForSubunit(NumMinimalSU);
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assert(MinimalPressure < SecondToMinimalPressure);
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const float Increment = SecondToMinimalPressure - MinimalPressure;
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if (RemainingPressure <= NumMinimalSU * Increment) {
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// There is not enough remaining pressure.
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for (size_t I = 0; I < NumMinimalSU; ++I) {
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getPressureForSubunit(I) += RemainingPressure / NumMinimalSU;
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}
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return;
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}
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// Bump all minimal pressure subunits to `SecondToMinimalPressure`.
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for (size_t I = 0; I < NumMinimalSU; ++I) {
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getPressureForSubunit(I) = SecondToMinimalPressure;
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RemainingPressure -= SecondToMinimalPressure;
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}
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while (NumMinimalSU < Subunits.size() &&
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getPressureForSubunit(NumMinimalSU) == SecondToMinimalPressure) {
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++NumMinimalSU;
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}
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}
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}
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std::vector<std::pair<uint16_t, float>>
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computeIdealizedProcResPressure(const MCSchedModel &SM,
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SmallVector<MCWriteProcResEntry, 8> WPRS) {
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// DensePressure[I] is the port pressure for Proc Resource I.
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SmallVector<float, 32> DensePressure(SM.getNumProcResourceKinds());
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sort(WPRS, [](const MCWriteProcResEntry &A, const MCWriteProcResEntry &B) {
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return A.ProcResourceIdx < B.ProcResourceIdx;
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});
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for (const MCWriteProcResEntry &WPR : WPRS) {
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// Get units for the entry.
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const MCProcResourceDesc *const ProcResDesc =
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SM.getProcResource(WPR.ProcResourceIdx);
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if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
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// This is a ProcResUnit.
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DensePressure[WPR.ProcResourceIdx] += WPR.Cycles;
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} else {
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// This is a ProcResGroup.
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SmallVector<uint16_t, 32> Subunits(ProcResDesc->SubUnitsIdxBegin,
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ProcResDesc->SubUnitsIdxBegin +
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ProcResDesc->NumUnits);
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distributePressure(WPR.Cycles, Subunits, DensePressure);
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}
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}
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// Turn dense pressure into sparse pressure by removing zero entries.
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std::vector<std::pair<uint16_t, float>> Pressure;
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for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
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if (DensePressure[I] > 0.0f)
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Pressure.emplace_back(I, DensePressure[I]);
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}
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return Pressure;
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}
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ResolvedSchedClass::ResolvedSchedClass(const MCSubtargetInfo &STI,
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unsigned ResolvedSchedClassId,
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bool WasVariant)
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: SchedClassId(ResolvedSchedClassId),
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SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)),
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WasVariant(WasVariant),
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NonRedundantWriteProcRes(getNonRedundantWriteProcRes(*SCDesc, STI)),
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IdealizedProcResPressure(computeIdealizedProcResPressure(
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STI.getSchedModel(), NonRedundantWriteProcRes)) {
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assert((SCDesc == nullptr || !SCDesc->isVariant()) &&
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"ResolvedSchedClass should never be variant");
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}
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static unsigned ResolveVariantSchedClassId(const MCSubtargetInfo &STI,
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const MCInstrInfo &InstrInfo,
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unsigned SchedClassId,
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const MCInst &MCI) {
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const auto &SM = STI.getSchedModel();
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while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant()) {
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SchedClassId = STI.resolveVariantSchedClass(SchedClassId, &MCI, &InstrInfo,
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SM.getProcessorID());
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}
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return SchedClassId;
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}
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std::pair<unsigned /*SchedClassId*/, bool /*WasVariant*/>
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ResolvedSchedClass::resolveSchedClassId(const MCSubtargetInfo &SubtargetInfo,
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const MCInstrInfo &InstrInfo,
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const MCInst &MCI) {
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unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
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const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel()
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.getSchedClassDesc(SchedClassId)
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->isVariant();
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SchedClassId =
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ResolveVariantSchedClassId(SubtargetInfo, InstrInfo, SchedClassId, MCI);
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return std::make_pair(SchedClassId, WasVariant);
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}
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// Returns a ProxResIdx by id or name.
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static unsigned findProcResIdx(const MCSubtargetInfo &STI,
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const StringRef NameOrId) {
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// Interpret the key as an ProcResIdx.
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unsigned ProcResIdx = 0;
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if (to_integer(NameOrId, ProcResIdx, 10))
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return ProcResIdx;
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// Interpret the key as a ProcRes name.
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const auto &SchedModel = STI.getSchedModel();
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for (int I = 0, E = SchedModel.getNumProcResourceKinds(); I < E; ++I) {
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if (NameOrId == SchedModel.getProcResource(I)->Name)
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return I;
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}
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return 0;
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}
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std::vector<BenchmarkMeasure> ResolvedSchedClass::getAsPoint(
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InstructionBenchmark::ModeE Mode, const MCSubtargetInfo &STI,
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ArrayRef<PerInstructionStats> Representative) const {
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const size_t NumMeasurements = Representative.size();
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std::vector<BenchmarkMeasure> SchedClassPoint(NumMeasurements);
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if (Mode == InstructionBenchmark::Latency) {
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assert(NumMeasurements == 1 && "Latency is a single measure.");
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BenchmarkMeasure &LatencyMeasure = SchedClassPoint[0];
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// Find the latency.
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LatencyMeasure.PerInstructionValue = 0.0;
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for (unsigned I = 0; I < SCDesc->NumWriteLatencyEntries; ++I) {
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const MCWriteLatencyEntry *const WLE =
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STI.getWriteLatencyEntry(SCDesc, I);
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LatencyMeasure.PerInstructionValue =
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std::max<double>(LatencyMeasure.PerInstructionValue, WLE->Cycles);
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}
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} else if (Mode == InstructionBenchmark::Uops) {
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for (auto I : zip(SchedClassPoint, Representative)) {
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BenchmarkMeasure &Measure = std::get<0>(I);
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const PerInstructionStats &Stats = std::get<1>(I);
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StringRef Key = Stats.key();
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uint16_t ProcResIdx = findProcResIdx(STI, Key);
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if (ProcResIdx > 0) {
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// Find the pressure on ProcResIdx `Key`.
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const auto ProcResPressureIt =
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llvm::find_if(IdealizedProcResPressure,
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[ProcResIdx](const std::pair<uint16_t, float> &WPR) {
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return WPR.first == ProcResIdx;
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});
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Measure.PerInstructionValue =
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ProcResPressureIt == IdealizedProcResPressure.end()
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? 0.0
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: ProcResPressureIt->second;
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} else if (Key == "NumMicroOps") {
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Measure.PerInstructionValue = SCDesc->NumMicroOps;
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} else {
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errs() << "expected `key` to be either a ProcResIdx or a ProcRes "
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"name, got "
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<< Key << "\n";
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return {};
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}
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}
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} else if (Mode == InstructionBenchmark::InverseThroughput) {
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assert(NumMeasurements == 1 && "Inverse Throughput is a single measure.");
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BenchmarkMeasure &RThroughputMeasure = SchedClassPoint[0];
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RThroughputMeasure.PerInstructionValue =
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MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
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} else {
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llvm_unreachable("unimplemented measurement matching mode");
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}
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return SchedClassPoint;
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}
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} // namespace exegesis
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} // namespace llvm
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