222 lines
9.9 KiB
C
222 lines
9.9 KiB
C
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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#include <arm_mve.h>
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// CHECK-LABEL: @test_vshlcq_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 18)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 1
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// CHECK-NEXT: ret <16 x i8> [[TMP3]]
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//
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int8x16_t test_vshlcq_s8(int8x16_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 18);
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#else /* POLYMORPHIC */
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return vshlcq_s8(a, b, 18);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 16)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 1
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// CHECK-NEXT: ret <8 x i16> [[TMP3]]
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//
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int16x8_t test_vshlcq_s16(int16x8_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 16);
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#else /* POLYMORPHIC */
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return vshlcq_s16(a, b, 16);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 4)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 1
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// CHECK-NEXT: ret <4 x i32> [[TMP3]]
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//
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int32x4_t test_vshlcq_s32(int32x4_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 4);
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#else /* POLYMORPHIC */
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return vshlcq_s32(a, b, 4);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 17)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 1
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// CHECK-NEXT: ret <16 x i8> [[TMP3]]
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//
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uint8x16_t test_vshlcq_u8(uint8x16_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 17);
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#else /* POLYMORPHIC */
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return vshlcq_u8(a, b, 17);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 17)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 1
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// CHECK-NEXT: ret <8 x i16> [[TMP3]]
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//
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uint16x8_t test_vshlcq_u16(uint16x8_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 17);
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#else /* POLYMORPHIC */
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return vshlcq_u16(a, b, 17);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 20)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 0
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 1
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// CHECK-NEXT: ret <4 x i32> [[TMP3]]
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//
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uint32x4_t test_vshlcq_u32(uint32x4_t a, uint32_t *b) {
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#ifdef POLYMORPHIC
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return vshlcq(a, b, 20);
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#else /* POLYMORPHIC */
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return vshlcq_u32(a, b, 20);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 29, <16 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 1
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// CHECK-NEXT: ret <16 x i8> [[TMP5]]
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//
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int8x16_t test_vshlcq_m_s8(int8x16_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 29, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_s8(a, b, 29, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 17, <8 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 1
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// CHECK-NEXT: ret <8 x i16> [[TMP5]]
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//
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int16x8_t test_vshlcq_m_s16(int16x8_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 17, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_s16(a, b, 17, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 9, <4 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 1
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// CHECK-NEXT: ret <4 x i32> [[TMP5]]
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//
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int32x4_t test_vshlcq_m_s32(int32x4_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 9, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_s32(a, b, 9, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 21, <16 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 1
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// CHECK-NEXT: ret <16 x i8> [[TMP5]]
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//
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uint8x16_t test_vshlcq_m_u8(uint8x16_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 21, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_u8(a, b, 21, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 24, <8 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 1
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// CHECK-NEXT: ret <8 x i16> [[TMP5]]
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//
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uint16x8_t test_vshlcq_m_u16(uint16x8_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 24, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_u16(a, b, 24, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vshlcq_m_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 26, <4 x i1> [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 0
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// CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4
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// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 1
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// CHECK-NEXT: ret <4 x i32> [[TMP5]]
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//
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uint32x4_t test_vshlcq_m_u32(uint32x4_t a, uint32_t *b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vshlcq_m(a, b, 26, p);
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#else /* POLYMORPHIC */
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return vshlcq_m_u32(a, b, 26, p);
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#endif /* POLYMORPHIC */
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}
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