432 lines
18 KiB
C
432 lines
18 KiB
C
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// RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -triple riscv32 -emit-llvm -fforce-enable-int128 %s -o - \
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// RUN: | FileCheck %s -check-prefixes=CHECK,CHECK-FORCEINT128
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// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// This file contains test cases that will have the same output for the ilp32,
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// ilp32f, and ilp32d ABIs.
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#include <stddef.h>
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#include <stdint.h>
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// CHECK-LABEL: define{{.*}} void @f_void()
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void f_void(void) {}
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// Scalar arguments and return values smaller than the word size are extended
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// according to the sign of their type, up to 32 bits
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// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 zeroext %x)
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_Bool f_scalar_0(_Bool x) { return x; }
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// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 signext %x)
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int8_t f_scalar_1(int8_t x) { return x; }
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// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 zeroext %x)
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uint8_t f_scalar_2(uint8_t x) { return x; }
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// CHECK-LABEL: define{{.*}} i32 @f_scalar_3(i32 %x)
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int32_t f_scalar_3(int32_t x) { return x; }
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// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 %x)
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int64_t f_scalar_4(int64_t x) { return x; }
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#ifdef __SIZEOF_INT128__
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// CHECK-FORCEINT128-LABEL: define{{.*}} i128 @f_scalar_5(i128 %x)
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__int128_t f_scalar_5(__int128_t x) { return x; }
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#endif
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// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float %x)
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float f_fp_scalar_1(float x) { return x; }
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// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double %x)
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double f_fp_scalar_2(double x) { return x; }
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// Scalars larger than 2*xlen are passed/returned indirect. However, the
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// RISC-V LLVM backend can handle this fine, so the function doesn't need to
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// be modified.
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// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 %x)
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long double f_fp_scalar_3(long double x) { return x; }
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// Empty structs or unions are ignored.
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struct empty_s {};
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// CHECK-LABEL: define{{.*}} void @f_agg_empty_struct()
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struct empty_s f_agg_empty_struct(struct empty_s x) {
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return x;
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}
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union empty_u {};
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// CHECK-LABEL: define{{.*}} void @f_agg_empty_union()
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union empty_u f_agg_empty_union(union empty_u x) {
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return x;
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}
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// Aggregates <= 2*xlen may be passed in registers, so will be coerced to
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// integer arguments. The rules for return are the same.
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struct tiny {
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uint8_t a, b, c, d;
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};
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// CHECK-LABEL: define{{.*}} void @f_agg_tiny(i32 %x.coerce)
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void f_agg_tiny(struct tiny x) {
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x.a += x.b;
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x.c += x.d;
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}
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// CHECK-LABEL: define{{.*}} i32 @f_agg_tiny_ret()
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struct tiny f_agg_tiny_ret() {
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return (struct tiny){1, 2, 3, 4};
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}
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typedef uint8_t v4i8 __attribute__((vector_size(4)));
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typedef int32_t v1i32 __attribute__((vector_size(4)));
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// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i8(i32 %x.coerce)
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void f_vec_tiny_v4i8(v4i8 x) {
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x[0] = x[1];
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x[2] = x[3];
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}
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// CHECK-LABEL: define{{.*}} i32 @f_vec_tiny_v4i8_ret()
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v4i8 f_vec_tiny_v4i8_ret() {
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return (v4i8){1, 2, 3, 4};
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}
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// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i32(i32 %x.coerce)
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void f_vec_tiny_v1i32(v1i32 x) {
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x[0] = 114;
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}
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// CHECK-LABEL: define{{.*}} i32 @f_vec_tiny_v1i32_ret()
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v1i32 f_vec_tiny_v1i32_ret() {
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return (v1i32){1};
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}
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struct small {
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int32_t a, *b;
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};
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// CHECK-LABEL: define{{.*}} void @f_agg_small([2 x i32] %x.coerce)
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void f_agg_small(struct small x) {
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x.a += *x.b;
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x.b = &x.a;
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}
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// CHECK-LABEL: define{{.*}} [2 x i32] @f_agg_small_ret()
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struct small f_agg_small_ret() {
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return (struct small){1, 0};
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}
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typedef uint8_t v8i8 __attribute__((vector_size(8)));
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typedef int64_t v1i64 __attribute__((vector_size(8)));
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// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i8(i64 %x.coerce)
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void f_vec_small_v8i8(v8i8 x) {
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x[0] = x[7];
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}
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// CHECK-LABEL: define{{.*}} i64 @f_vec_small_v8i8_ret()
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v8i8 f_vec_small_v8i8_ret() {
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return (v8i8){1, 2, 3, 4, 5, 6, 7, 8};
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}
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// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i64(i64 %x.coerce)
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void f_vec_small_v1i64(v1i64 x) {
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x[0] = 114;
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}
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// CHECK-LABEL: define{{.*}} i64 @f_vec_small_v1i64_ret()
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v1i64 f_vec_small_v1i64_ret() {
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return (v1i64){1};
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}
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// Aggregates of 2*xlen size and 2*xlen alignment should be coerced to a
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// single 2*xlen-sized argument, to ensure that alignment can be maintained if
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// passed on the stack.
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struct small_aligned {
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int64_t a;
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};
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// CHECK-LABEL: define{{.*}} void @f_agg_small_aligned(i64 %x.coerce)
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void f_agg_small_aligned(struct small_aligned x) {
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x.a += x.a;
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}
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// CHECK-LABEL: define{{.*}} i64 @f_agg_small_aligned_ret(i64 %x.coerce)
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struct small_aligned f_agg_small_aligned_ret(struct small_aligned x) {
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return (struct small_aligned){10};
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}
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// Aggregates greater > 2*xlen will be passed and returned indirectly
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struct large {
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int32_t a, b, c, d;
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};
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// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x)
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void f_agg_large(struct large x) {
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x.a = x.b + x.c + x.d;
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}
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// The address where the struct should be written to will be the first
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// argument
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// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %i, i8 signext %j)
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struct large f_agg_large_ret(int32_t i, int8_t j) {
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return (struct large){1, 2, 3, 4};
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}
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typedef unsigned char v16i8 __attribute__((vector_size(16)));
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// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8(<16 x i8>* %0)
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void f_vec_large_v16i8(v16i8 x) {
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x[0] = x[7];
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}
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// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8_ret(<16 x i8>* noalias sret(<16 x i8>) align 16 %agg.result)
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v16i8 f_vec_large_v16i8_ret() {
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return (v16i8){1, 2, 3, 4, 5, 6, 7, 8};
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}
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// Scalars passed on the stack should not have signext/zeroext attributes
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// (they are anyext).
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// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a.coerce, [2 x i32] %b.coerce, i64 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h)
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int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c,
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struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) {
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return g + h;
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}
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// Ensure that scalars passed on the stack are still determined correctly in
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// the presence of large return values that consume a register due to the need
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// to pass a pointer.
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// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
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struct large f_scalar_stack_2(int32_t a, int64_t b, int64_t c, long double d,
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uint8_t e, int8_t f, uint8_t g) {
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return (struct large){a, e, f, g};
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}
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// CHECK-LABEL: define{{.*}} fp128 @f_scalar_stack_4(i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
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long double f_scalar_stack_4(int32_t a, int64_t b, int64_t c, long double d,
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uint8_t e, int8_t f, uint8_t g) {
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return d;
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}
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// Aggregates and >=XLen scalars passed on the stack should be lowered just as
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// they would be if passed via registers.
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// CHECK-LABEL: define{{.*}} void @f_scalar_stack_5(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, float %g, double %h, fp128 %i)
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void f_scalar_stack_5(double a, int64_t b, double c, int64_t d, int e,
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int64_t f, float g, double h, long double i) {}
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// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h)
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void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e,
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struct small f, struct small_aligned g, struct large h) {}
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// Ensure that ABI lowering happens as expected for vararg calls. For RV32
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// with the base integer calling convention there will be no observable
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// differences in the lowered IR for a call with varargs vs without.
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int f_va_callee(int, ...);
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// CHECK-LABEL: define{{.*}} void @f_va_caller()
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// CHECK: call i32 (i32, ...) @f_va_callee(i32 1, i32 2, i64 3, double 4.000000e+00, double 5.000000e+00, i32 {{%.*}}, [2 x i32] {{%.*}}, i64 {{%.*}}, %struct.large* {{%.*}})
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void f_va_caller() {
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f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9},
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(struct small){10, NULL}, (struct small_aligned){11},
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(struct large){12, 13, 14, 15});
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}
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// CHECK-LABEL: define{{.*}} i32 @f_va_1(i8* %fmt, ...) {{.*}} {
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// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
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// CHECK: [[VA:%.*]] = alloca i8*, align 4
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// CHECK: [[V:%.*]] = alloca i32, align 4
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// CHECK: store i8* %fmt, i8** [[FMT_ADDR]], align 4
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// CHECK: [[VA1:%.*]] = bitcast i8** [[VA]] to i8*
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// CHECK: call void @llvm.va_start(i8* [[VA1]])
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// CHECK: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4
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// CHECK: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4
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// CHECK: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
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// CHECK: [[TMP0:%.*]] = bitcast i8* [[ARGP_CUR]] to i32*
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// CHECK: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
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// CHECK: store i32 [[TMP1]], i32* [[V]], align 4
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// CHECK: [[VA2:%.*]] = bitcast i8** [[VA]] to i8*
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// CHECK: call void @llvm.va_end(i8* [[VA2]])
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// CHECK: [[TMP2:%.*]] = load i32, i32* [[V]], align 4
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// CHECK: ret i32 [[TMP2]]
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// CHECK: }
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int f_va_1(char *fmt, ...) {
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__builtin_va_list va;
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__builtin_va_start(va, fmt);
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int v = __builtin_va_arg(va, int);
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__builtin_va_end(va);
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return v;
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}
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// An "aligned" register pair (where the first register is even-numbered) is
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// used to pass varargs with 2x xlen alignment and 2x xlen size. Ensure the
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// correct offsets are used.
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// CHECK-LABEL: @f_va_2(
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// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
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// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4
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// CHECK-NEXT: [[V:%.*]] = alloca double, align 8
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// CHECK-NEXT: store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 4
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// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8*
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// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]])
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// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[ARGP_CUR]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 7
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// CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
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// CHECK-NEXT: [[ARGP_CUR_ALIGNED:%.*]] = inttoptr i32 [[TMP2]] to i8*
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// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR_ALIGNED]], i32 8
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// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[ARGP_CUR_ALIGNED]] to double*
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// CHECK-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8
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// CHECK-NEXT: store double [[TMP4]], double* [[V]], align 8
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// CHECK-NEXT: [[VA2:%.*]] = bitcast i8** [[VA]] to i8*
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// CHECK-NEXT: call void @llvm.va_end(i8* [[VA2]])
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// CHECK-NEXT: [[TMP5:%.*]] = load double, double* [[V]], align 8
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// CHECK-NEXT: ret double [[TMP5]]
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|
|
double f_va_2(char *fmt, ...) {
|
||
|
|
__builtin_va_list va;
|
||
|
|
|
||
|
|
__builtin_va_start(va, fmt);
|
||
|
|
double v = __builtin_va_arg(va, double);
|
||
|
|
__builtin_va_end(va);
|
||
|
|
|
||
|
|
return v;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Two "aligned" register pairs.
|
||
|
|
|
||
|
|
// CHECK-LABEL: @f_va_3(
|
||
|
|
// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
|
||
|
|
// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4
|
||
|
|
// CHECK-NEXT: [[V:%.*]] = alloca double, align 8
|
||
|
|
// CHECK-NEXT: [[W:%.*]] = alloca i32, align 4
|
||
|
|
// CHECK-NEXT: [[X:%.*]] = alloca double, align 8
|
||
|
|
// CHECK-NEXT: store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 4
|
||
|
|
// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]])
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[ARGP_CUR]] to i32
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 7
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR_ALIGNED:%.*]] = inttoptr i32 [[TMP2]] to i8*
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR_ALIGNED]], i32 8
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[ARGP_CUR_ALIGNED]] to double*
|
||
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load double, double* [[TMP3]], align 8
|
||
|
|
// CHECK-NEXT: store double [[TMP4]], double* [[V]], align 8
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR2:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT3:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR2]], i32 4
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT3]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[ARGP_CUR2]] to i32*
|
||
|
|
// CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
||
|
|
// CHECK-NEXT: store i32 [[TMP6]], i32* [[W]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR4:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP7:%.*]] = ptrtoint i8* [[ARGP_CUR4]] to i32
|
||
|
|
// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], 7
|
||
|
|
// CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], -8
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR4_ALIGNED:%.*]] = inttoptr i32 [[TMP9]] to i8*
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT5:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR4_ALIGNED]], i32 8
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT5]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[ARGP_CUR4_ALIGNED]] to double*
|
||
|
|
// CHECK-NEXT: [[TMP11:%.*]] = load double, double* [[TMP10]], align 8
|
||
|
|
// CHECK-NEXT: store double [[TMP11]], double* [[X]], align 8
|
||
|
|
// CHECK-NEXT: [[VA6:%.*]] = bitcast i8** [[VA]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.va_end(i8* [[VA6]])
|
||
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load double, double* [[V]], align 8
|
||
|
|
// CHECK-NEXT: [[TMP13:%.*]] = load double, double* [[X]], align 8
|
||
|
|
// CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP12]], [[TMP13]]
|
||
|
|
// CHECK-NEXT: ret double [[ADD]]
|
||
|
|
double f_va_3(char *fmt, ...) {
|
||
|
|
__builtin_va_list va;
|
||
|
|
|
||
|
|
__builtin_va_start(va, fmt);
|
||
|
|
double v = __builtin_va_arg(va, double);
|
||
|
|
int w = __builtin_va_arg(va, int);
|
||
|
|
double x = __builtin_va_arg(va, double);
|
||
|
|
__builtin_va_end(va);
|
||
|
|
|
||
|
|
return v + x;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: define{{.*}} i32 @f_va_4(i8* %fmt, ...) {{.*}} {
|
||
|
|
// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
|
||
|
|
// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4
|
||
|
|
// CHECK-NEXT: [[V:%.*]] = alloca i32, align 4
|
||
|
|
// CHECK-NEXT: [[LD:%.*]] = alloca fp128, align 16
|
||
|
|
// CHECK-NEXT: [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
|
||
|
|
// CHECK-NEXT: [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
|
||
|
|
// CHECK-NEXT: [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
|
||
|
|
// CHECK-NEXT: [[RET:%.*]] = alloca i32, align 4
|
||
|
|
// CHECK-NEXT: store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 4
|
||
|
|
// CHECK-NEXT: [[VA1:%.*]] = bitcast i8** [[VA]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.va_start(i8* [[VA1]])
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR]], i32 4
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[ARGP_CUR]] to i32*
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
||
|
|
// CHECK-NEXT: store i32 [[TMP1]], i32* [[V]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR2:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT3:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR2]], i32 4
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT3]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[ARGP_CUR2]] to fp128**
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load fp128*, fp128** [[TMP2]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load fp128, fp128* [[TMP3]], align 16
|
||
|
|
// CHECK-NEXT: store fp128 [[TMP4]], fp128* [[LD]], align 16
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR4:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT5:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR4]], i32 4
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT5]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[ARGP_CUR4]] to %struct.tiny*
|
||
|
|
// CHECK-NEXT: [[TMP6:%.*]] = bitcast %struct.tiny* [[TS]] to i8*
|
||
|
|
// CHECK-NEXT: [[TMP7:%.*]] = bitcast %struct.tiny* [[TMP5]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false)
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR6:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT7:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR6]], i32 8
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT7]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[ARGP_CUR6]] to %struct.small*
|
||
|
|
// CHECK-NEXT: [[TMP9:%.*]] = bitcast %struct.small* [[SS]] to i8*
|
||
|
|
// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct.small* [[TMP8]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 8, i1 false)
|
||
|
|
// CHECK-NEXT: [[ARGP_CUR8:%.*]] = load i8*, i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[ARGP_NEXT9:%.*]] = getelementptr inbounds i8, i8* [[ARGP_CUR8]], i32 4
|
||
|
|
// CHECK-NEXT: store i8* [[ARGP_NEXT9]], i8** [[VA]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP11:%.*]] = bitcast i8* [[ARGP_CUR8]] to %struct.large**
|
||
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load %struct.large*, %struct.large** [[TMP11]], align 4
|
||
|
|
// CHECK-NEXT: [[TMP13:%.*]] = bitcast %struct.large* [[LS]] to i8*
|
||
|
|
// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.large* [[TMP12]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 16, i1 false)
|
||
|
|
// CHECK-NEXT: [[VA10:%.*]] = bitcast i8** [[VA]] to i8*
|
||
|
|
// CHECK-NEXT: call void @llvm.va_end(i8* [[VA10]])
|
||
|
|
int f_va_4(char *fmt, ...) {
|
||
|
|
__builtin_va_list va;
|
||
|
|
|
||
|
|
__builtin_va_start(va, fmt);
|
||
|
|
int v = __builtin_va_arg(va, int);
|
||
|
|
long double ld = __builtin_va_arg(va, long double);
|
||
|
|
struct tiny ts = __builtin_va_arg(va, struct tiny);
|
||
|
|
struct small ss = __builtin_va_arg(va, struct small);
|
||
|
|
struct large ls = __builtin_va_arg(va, struct large);
|
||
|
|
__builtin_va_end(va);
|
||
|
|
|
||
|
|
int ret = (int)((long double)v + ld);
|
||
|
|
ret = ret + ts.a + ts.b + ts.c + ts.d;
|
||
|
|
ret = ret + ss.a + (int)ss.b;
|
||
|
|
ret = ret + ls.a + ls.b + ls.c + ls.d;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|