69 lines
2.9 KiB
C
69 lines
2.9 KiB
C
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// RUN: %clang_cc1 -triple riscv32 -O1 -emit-llvm %s -o - \
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// RUN: | FileCheck %s -check-prefix=RV32I
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// RUN: %clang_cc1 -triple riscv32 -target-feature +a -O1 -emit-llvm %s -o - \
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// RUN: | FileCheck %s -check-prefix=RV32IA
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// RUN: %clang_cc1 -triple riscv64 -O1 -emit-llvm %s -o - \
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// RUN: | FileCheck %s -check-prefix=RV64I
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// RUN: %clang_cc1 -triple riscv64 -target-feature +a -O1 -emit-llvm %s -o - \
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// RUN: | FileCheck %s -check-prefix=RV64IA
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// This test demonstrates that MaxAtomicInlineWidth is set appropriately when
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// the atomics instruction set extension is enabled.
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#include <stdatomic.h>
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#include <stdint.h>
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void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) {
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// RV32I: call zeroext i8 @__atomic_load_1
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// RV32I: call void @__atomic_store_1
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// RV32I: call zeroext i8 @__atomic_fetch_add_1
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// RV32IA: load atomic i8, i8* %a seq_cst, align 1
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// RV32IA: store atomic i8 %b, i8* %a seq_cst, align 1
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// RV32IA: atomicrmw add i8* %a, i8 %b seq_cst
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// RV64I: call zeroext i8 @__atomic_load_1
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// RV64I: call void @__atomic_store_1
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// RV64I: call zeroext i8 @__atomic_fetch_add_1
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// RV64IA: load atomic i8, i8* %a seq_cst, align 1
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// RV64IA: store atomic i8 %b, i8* %a seq_cst, align 1
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// RV64IA: atomicrmw add i8* %a, i8 %b seq_cst
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__c11_atomic_load(a, memory_order_seq_cst);
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__c11_atomic_store(a, b, memory_order_seq_cst);
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__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
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}
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void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) {
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// RV32I: call i32 @__atomic_load_4
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// RV32I: call void @__atomic_store_4
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// RV32I: call i32 @__atomic_fetch_add_4
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// RV32IA: load atomic i32, i32* %a seq_cst, align 4
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// RV32IA: store atomic i32 %b, i32* %a seq_cst, align 4
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// RV32IA: atomicrmw add i32* %a, i32 %b seq_cst
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// RV64I: call signext i32 @__atomic_load_4
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// RV64I: call void @__atomic_store_4
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// RV64I: call signext i32 @__atomic_fetch_add_4
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// RV64IA: load atomic i32, i32* %a seq_cst, align 4
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// RV64IA: store atomic i32 %b, i32* %a seq_cst, align 4
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// RV64IA: atomicrmw add i32* %a, i32 %b seq_cst
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__c11_atomic_load(a, memory_order_seq_cst);
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__c11_atomic_store(a, b, memory_order_seq_cst);
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__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
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}
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void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) {
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// RV32I: call i64 @__atomic_load_8
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// RV32I: call void @__atomic_store_8
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// RV32I: call i64 @__atomic_fetch_add_8
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// RV32IA: call i64 @__atomic_load_8
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// RV32IA: call void @__atomic_store_8
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// RV32IA: call i64 @__atomic_fetch_add_8
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// RV64I: call i64 @__atomic_load_8
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// RV64I: call void @__atomic_store_8
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// RV64I: call i64 @__atomic_fetch_add_8
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// RV64IA: load atomic i64, i64* %a seq_cst, align 8
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// RV64IA: store atomic i64 %b, i64* %a seq_cst, align 8
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// RV64IA: atomicrmw add i64* %a, i64 %b seq_cst
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__c11_atomic_load(a, memory_order_seq_cst);
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__c11_atomic_store(a, b, memory_order_seq_cst);
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__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
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}
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