424 lines
16 KiB
LLVM
424 lines
16 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=thumbv8m.main %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
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; RUN: opt -mtriple=thumbv8a %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
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; RUN: opt -mtriple=armv8a %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
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define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.false, label %cond.end
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @foo_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
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; CHECK-LABEL: @foo_minsize(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.false, label %cond.end
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @foo_minsize_i64(i64 %a, i64 %b, i64 %c, i64 %d, i32* %input) #0 {
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; CHECK-LABEL: @foo_minsize_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[D:%.*]], 3
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i64 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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lor.lhs.false:
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%add = add nsw i64 %c, %a
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%cmp1 = icmp slt i64 %add, %b
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br i1 %cmp1, label %cond.false, label %cond.end
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @or_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
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; CHECK-LABEL: @or_predicate(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.end, label %cond.false
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @or_invert_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) {
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; CHECK-LABEL: @or_invert_predicate(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %lor.lhs.false, label %cond.end
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.end, label %cond.false
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @or_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
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; THUMB-LABEL: @or_predicate_minsize(
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; THUMB-NEXT: entry:
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; THUMB-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
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; THUMB-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; THUMB: lor.lhs.false:
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; THUMB-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; THUMB-NEXT: br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
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; THUMB: cond.false:
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; THUMB-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; THUMB-NEXT: br label [[COND_END]]
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; THUMB: cond.end:
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; THUMB-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; THUMB-NEXT: ret i32 [[COND]]
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;
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; ARM-LABEL: @or_predicate_minsize(
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; ARM-NEXT: entry:
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; ARM-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
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; ARM-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; ARM-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
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; ARM-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; ARM: cond.false:
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; ARM-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; ARM-NEXT: br label [[COND_END]]
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; ARM: cond.end:
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; ARM-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; ARM-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.end, label %cond.false
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @or_invert_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input) #0 {
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; THUMB-LABEL: @or_invert_predicate_minsize(
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; THUMB-NEXT: entry:
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; THUMB-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 3
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; THUMB-NEXT: br i1 [[CMP]], label [[LOR_LHS_FALSE:%.*]], label [[COND_END:%.*]]
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; THUMB: lor.lhs.false:
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; THUMB-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; THUMB-NEXT: br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
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; THUMB: cond.false:
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; THUMB-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; THUMB-NEXT: br label [[COND_END]]
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; THUMB: cond.end:
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; THUMB-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; THUMB-NEXT: ret i32 [[COND]]
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;
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; ARM-LABEL: @or_invert_predicate_minsize(
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; ARM-NEXT: entry:
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; ARM-NEXT: [[CMP:%.*]] = icmp sle i32 [[D:%.*]], 3
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; ARM-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; ARM-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
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; ARM-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; ARM: cond.false:
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; ARM-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; ARM-NEXT: br label [[COND_END]]
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; ARM: cond.end:
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; ARM-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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; ARM-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %lor.lhs.false, label %cond.end
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lor.lhs.false:
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%add = add nsw i32 %c, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.end, label %cond.false
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cond.false:
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%0 = load i32, i32* %input, align 4
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
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ret i32 %cond
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}
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define i32 @or_xor_predicate(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) {
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; CHECK-LABEL: @or_xor_predicate(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
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; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP_NOT]], [[CMP1]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
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|
; CHECK-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
br i1 %cmp, label %lor.lhs.false, label %cond.end
|
||
|
|
|
||
|
|
lor.lhs.false:
|
||
|
|
%add = add nsw i32 %c, %a
|
||
|
|
%cmp1 = icmp slt i32 %add, %b
|
||
|
|
br i1 %cmp1, label %cond.end, label %cond.false
|
||
|
|
|
||
|
|
cond.false:
|
||
|
|
%0 = load i32, i32* %input, align 4
|
||
|
|
br label %cond.end
|
||
|
|
|
||
|
|
cond.end:
|
||
|
|
%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
|
||
|
|
ret i32 %cond
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @or_xor_predicate_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) #0 {
|
||
|
|
; THUMB-LABEL: @or_xor_predicate_minsize(
|
||
|
|
; THUMB-NEXT: entry:
|
||
|
|
; THUMB-NEXT: br i1 [[CMP:%.*]], label [[LOR_LHS_FALSE:%.*]], label [[COND_END:%.*]]
|
||
|
|
; THUMB: lor.lhs.false:
|
||
|
|
; THUMB-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
|
||
|
|
; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
|
||
|
|
; THUMB-NEXT: br i1 [[CMP1]], label [[COND_END]], label [[COND_FALSE:%.*]]
|
||
|
|
; THUMB: cond.false:
|
||
|
|
; THUMB-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
|
||
|
|
; THUMB-NEXT: br label [[COND_END]]
|
||
|
|
; THUMB: cond.end:
|
||
|
|
; THUMB-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; THUMB-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
; ARM-LABEL: @or_xor_predicate_minsize(
|
||
|
|
; ARM-NEXT: entry:
|
||
|
|
; ARM-NEXT: [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
|
||
|
|
; ARM-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
|
||
|
|
; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
|
||
|
|
; ARM-NEXT: [[OR_COND:%.*]] = or i1 [[CMP_NOT]], [[CMP1]]
|
||
|
|
; ARM-NEXT: br i1 [[OR_COND]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
|
||
|
|
; ARM: cond.false:
|
||
|
|
; ARM-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
|
||
|
|
; ARM-NEXT: br label [[COND_END]]
|
||
|
|
; ARM: cond.end:
|
||
|
|
; ARM-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; ARM-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
br i1 %cmp, label %lor.lhs.false, label %cond.end
|
||
|
|
|
||
|
|
lor.lhs.false:
|
||
|
|
%add = add nsw i32 %c, %a
|
||
|
|
%cmp1 = icmp slt i32 %add, %b
|
||
|
|
br i1 %cmp1, label %cond.end, label %cond.false
|
||
|
|
|
||
|
|
cond.false:
|
||
|
|
%0 = load i32, i32* %input, align 4
|
||
|
|
br label %cond.end
|
||
|
|
|
||
|
|
cond.end:
|
||
|
|
%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
|
||
|
|
ret i32 %cond
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @and_xor(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) {
|
||
|
|
; CHECK-LABEL: @and_xor(
|
||
|
|
; CHECK-NEXT: entry:
|
||
|
|
; CHECK-NEXT: [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
|
||
|
|
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
|
||
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
|
||
|
|
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP_NOT]], [[CMP1]]
|
||
|
|
; CHECK-NEXT: br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
|
||
|
|
; CHECK: cond.false:
|
||
|
|
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
|
||
|
|
; CHECK-NEXT: br label [[COND_END]]
|
||
|
|
; CHECK: cond.end:
|
||
|
|
; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; CHECK-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
br i1 %cmp, label %cond.end, label %lor.lhs.false
|
||
|
|
|
||
|
|
lor.lhs.false:
|
||
|
|
%add = add nsw i32 %c, %a
|
||
|
|
%cmp1 = icmp slt i32 %add, %b
|
||
|
|
br i1 %cmp1, label %cond.false, label %cond.end
|
||
|
|
|
||
|
|
cond.false:
|
||
|
|
%0 = load i32, i32* %input, align 4
|
||
|
|
br label %cond.end
|
||
|
|
|
||
|
|
cond.end:
|
||
|
|
%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
|
||
|
|
ret i32 %cond
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @and_xor_minsize(i32 %a, i32 %b, i32 %c, i32 %d, i32* %input, i1 %cmp) #0 {
|
||
|
|
; THUMB-LABEL: @and_xor_minsize(
|
||
|
|
; THUMB-NEXT: entry:
|
||
|
|
; THUMB-NEXT: br i1 [[CMP:%.*]], label [[COND_END:%.*]], label [[LOR_LHS_FALSE:%.*]]
|
||
|
|
; THUMB: lor.lhs.false:
|
||
|
|
; THUMB-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
|
||
|
|
; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
|
||
|
|
; THUMB-NEXT: br i1 [[CMP1]], label [[COND_FALSE:%.*]], label [[COND_END]]
|
||
|
|
; THUMB: cond.false:
|
||
|
|
; THUMB-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
|
||
|
|
; THUMB-NEXT: br label [[COND_END]]
|
||
|
|
; THUMB: cond.end:
|
||
|
|
; THUMB-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[LOR_LHS_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; THUMB-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
; ARM-LABEL: @and_xor_minsize(
|
||
|
|
; ARM-NEXT: entry:
|
||
|
|
; ARM-NEXT: [[CMP_NOT:%.*]] = xor i1 [[CMP:%.*]], true
|
||
|
|
; ARM-NEXT: [[ADD:%.*]] = add nsw i32 [[C:%.*]], [[A:%.*]]
|
||
|
|
; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
|
||
|
|
; ARM-NEXT: [[OR_COND:%.*]] = and i1 [[CMP_NOT]], [[CMP1]]
|
||
|
|
; ARM-NEXT: br i1 [[OR_COND]], label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
|
||
|
|
; ARM: cond.false:
|
||
|
|
; ARM-NEXT: [[TMP0:%.*]] = load i32, i32* [[INPUT:%.*]], align 4
|
||
|
|
; ARM-NEXT: br label [[COND_END]]
|
||
|
|
; ARM: cond.end:
|
||
|
|
; ARM-NEXT: [[COND:%.*]] = phi i32 [ [[TMP0]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; ARM-NEXT: ret i32 [[COND]]
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
br i1 %cmp, label %cond.end, label %lor.lhs.false
|
||
|
|
|
||
|
|
lor.lhs.false:
|
||
|
|
%add = add nsw i32 %c, %a
|
||
|
|
%cmp1 = icmp slt i32 %add, %b
|
||
|
|
br i1 %cmp1, label %cond.false, label %cond.end
|
||
|
|
|
||
|
|
cond.false:
|
||
|
|
%0 = load i32, i32* %input, align 4
|
||
|
|
br label %cond.end
|
||
|
|
|
||
|
|
cond.end:
|
||
|
|
%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ], [ 0, %entry ]
|
||
|
|
ret i32 %cond
|
||
|
|
}
|
||
|
|
|
||
|
|
attributes #0 = { minsize optsize }
|