81 lines
3.5 KiB
LLVM
81 lines
3.5 KiB
LLVM
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; RUN: opt -mtriple=thumbv8.1m.main-arm-eabihf -mattr=+mve.fp -loop-vectorize -tail-predication=enabled -S < %s | \
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; RUN: FileCheck %s
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; Check that loop hint predicate.enable loop can overrule the TTI hook. For
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; this test case, the TTI hook rejects tail-predication:
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;
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; ARMHWLoops: Trip count does not fit into 32bits
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; preferPredicateOverEpilogue: hardware-loop is not profitable.
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;
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define dso_local void @tail_folding(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C) {
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; CHECK-LABEL: tail_folding(
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; CHECK: vector.body:
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; CHECK-NOT: call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(
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; CHECK-NOT: call void @llvm.masked.store.v4i32.p0v4i32(
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body
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entry:
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
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%1 = load i32, i32* %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %add, i32* %arrayidx4, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 430
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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; The same test case but now with predicate.enable = true should get
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; tail-folded.
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;
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define dso_local void @predicate_loop_hint(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C) {
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; CHECK-LABEL: predicate_loop_hint(
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; CHECK: vector.body:
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; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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; CHECK: %[[ELEM0:.*]] = add i64 %index, 0
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; CHECK: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %[[ELEM0]], i64 430)
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; CHECK: %[[WML1:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.*}}<4 x i1> %active.lane.mask
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; CHECK: %[[WML2:.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.*}}<4 x i1> %active.lane.mask
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; CHECK: %[[ADD:.*]] = add nsw <4 x i32> %[[WML2]], %[[WML1]]
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; CHECK: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %[[ADD]], {{.*}}<4 x i1> %active.lane.mask
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; CHECK: %index.next = add i64 %index, 4
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; CHECK: br i1 %{{.*}}, label %{{.*}}, label %vector.body
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entry:
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
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%1 = load i32, i32* %arrayidx2, align 4
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%add = add nsw i32 %1, %0
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%arrayidx4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %add, i32* %arrayidx4, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 430
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !6
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}
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; CHECK: !0 = distinct !{!0, !1}
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; CHECK-NEXT: !1 = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK-NEXT: !2 = distinct !{!2, !3, !1}
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; CHECK-NEXT: !3 = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK-NEXT: !4 = distinct !{!4, !1}
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; CHECK-NEXT: !5 = distinct !{!5, !3, !1}
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!6 = distinct !{!6, !7, !8}
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!7 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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!8 = !{!"llvm.loop.vectorize.enable", i1 true}
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