167 lines
5.9 KiB
LLVM
167 lines
5.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -loop-rotate < %s | FileCheck %s
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define i64 @switch_multi_entry_known_entry() {
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; CHECK-LABEL: @switch_multi_entry_known_entry(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ 2, [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]
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; CHECK-NEXT: switch i8 [[STATE]], label [[EXIT:%.*]] [
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; CHECK-NEXT: i8 0, label [[LATCH]]
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; CHECK-NEXT: i8 2, label [[LATCH]]
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; CHECK-NEXT: ]
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; CHECK: latch:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 999
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; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8
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; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ]
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; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]
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;
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start:
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br label %header
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header: ; preds = %latch, %start
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%state = phi i8 [ 2, %start ], [ %next_state, %latch ]
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%count = phi i64 [ 0, %start ], [ %inc, %latch ]
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switch i8 %state, label %exit [
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i8 0, label %latch
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i8 2, label %latch
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]
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latch: ; preds = %header, %header
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%cmp = icmp eq i64 %count, 999
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%next_state = zext i1 %cmp to i8
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%inc = add i64 %count, 1
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br label %header
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exit: ; preds = %header
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ret i64 %count
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}
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define i64 @switch_multi_entry_unknown_entry(i8 %start_state) {
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; CHECK-LABEL: @switch_multi_entry_unknown_entry(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ [[START_STATE:%.*]], [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]
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; CHECK-NEXT: switch i8 [[STATE]], label [[EXIT:%.*]] [
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; CHECK-NEXT: i8 0, label [[LATCH]]
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; CHECK-NEXT: i8 2, label [[LATCH]]
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; CHECK-NEXT: ]
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; CHECK: latch:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 999
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; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8
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; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ]
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; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]
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;
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start:
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br label %header
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header: ; preds = %latch, %start
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%state = phi i8 [ %start_state, %start ], [ %next_state, %latch ]
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%count = phi i64 [ 0, %start ], [ %inc, %latch ]
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switch i8 %state, label %exit [
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i8 0, label %latch
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i8 2, label %latch
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]
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latch: ; preds = %header, %header
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%cmp = icmp eq i64 %count, 999
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%next_state = zext i1 %cmp to i8
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%inc = add i64 %count, 1
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br label %header
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exit: ; preds = %header
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ret i64 %count
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}
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define i64 @switch_multi_exit_known_entry() {
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; CHECK-LABEL: @switch_multi_exit_known_entry(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ 0, [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]
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; CHECK-NEXT: switch i8 [[STATE]], label [[LATCH]] [
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; CHECK-NEXT: i8 1, label [[EXIT:%.*]]
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; CHECK-NEXT: i8 2, label [[EXIT]]
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; CHECK-NEXT: ]
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; CHECK: latch:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 999
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; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8
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; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ], [ [[COUNT]], [[HEADER]] ]
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; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]
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;
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start:
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br label %header
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header: ; preds = %latch, %start
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%state = phi i8 [ 0, %start ], [ %next_state, %latch ]
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%count = phi i64 [ 0, %start ], [ %inc, %latch ]
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switch i8 %state, label %latch [
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i8 1, label %exit
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i8 2, label %exit
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]
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latch: ; preds = %header, %header
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%cmp = icmp eq i64 %count, 999
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%next_state = zext i1 %cmp to i8
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%inc = add i64 %count, 1
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br label %header
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exit: ; preds = %header
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ret i64 %count
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}
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define i64 @switch_multi_exit_unknown_entry(i8 %start_state) {
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; CHECK-LABEL: @switch_multi_exit_unknown_entry(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[STATE:%.*]] = phi i8 [ [[START_STATE:%.*]], [[START:%.*]] ], [ [[NEXT_STATE:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ 0, [[START]] ], [ [[INC:%.*]], [[LATCH]] ]
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; CHECK-NEXT: switch i8 [[STATE]], label [[LATCH]] [
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; CHECK-NEXT: i8 1, label [[EXIT:%.*]]
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; CHECK-NEXT: i8 2, label [[EXIT]]
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; CHECK-NEXT: ]
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; CHECK: latch:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[COUNT]], 999
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; CHECK-NEXT: [[NEXT_STATE]] = zext i1 [[CMP]] to i8
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; CHECK-NEXT: [[INC]] = add i64 [[COUNT]], 1
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[COUNT_LCSSA:%.*]] = phi i64 [ [[COUNT]], [[HEADER]] ], [ [[COUNT]], [[HEADER]] ]
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; CHECK-NEXT: ret i64 [[COUNT_LCSSA]]
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;
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start:
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br label %header
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header: ; preds = %latch, %start
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%state = phi i8 [ %start_state, %start ], [ %next_state, %latch ]
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%count = phi i64 [ 0, %start ], [ %inc, %latch ]
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switch i8 %state, label %latch [
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i8 1, label %exit
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i8 2, label %exit
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]
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latch: ; preds = %header, %header
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%cmp = icmp eq i64 %count, 999
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%next_state = zext i1 %cmp to i8
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%inc = add i64 %count, 1
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br label %header
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exit: ; preds = %header
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ret i64 %count
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}
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