467 lines
10 KiB
LLVM
467 lines
10 KiB
LLVM
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; RUN: opt -S -basic-aa -licm -enable-mssa-loop-dependency=false %s -enable-new-pm=0 | FileCheck -check-prefixes=CHECK,AST %s
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; RUN: opt -S -basic-aa -licm -enable-mssa-loop-dependency=true %s -enable-new-pm=0 | FileCheck -check-prefixes=CHECK,MSSA %s
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; RUN: opt -aa-pipeline=basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop(licm)' < %s -S | FileCheck -check-prefixes=CHECK,AST %s
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; RUN: opt -aa-pipeline=basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop-mssa(licm)' < %s -S | FileCheck -check-prefixes=CHECK,MSSA %s
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define void @test(i32* %loc) {
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; CHECK-LABEL: @test
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; CHECK-LABEL: entry:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: loop:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_multiexit(i32* %loc, i1 %earlycnd) {
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; CHECK-LABEL: @test_multiexit
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; CHECK-LABEL: entry:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: loop:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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store i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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br i1 %earlycnd, label %exit1, label %backedge
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backedge:
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit2
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exit1:
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ret void
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exit2:
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ret void
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}
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define i32* @false_negative_2use(i32* %loc) {
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; CHECK-LABEL: @false_negative_2use
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; AST-LABEL: exit:
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; AST: store i32 0, i32* %loc
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; MSSA-LABEL: entry:
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; MSSA: store i32 0, i32* %loc
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; MSSA-LABEL: loop:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32* %loc
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}
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define void @neg_lv_value(i32* %loc) {
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; CHECK-LABEL: @neg_lv_value
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; CHECK-LABEL: exit:
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; CHECK: store i32 %iv.lcssa, i32* %loc
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 %iv, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_lv_addr(i32* %loc) {
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; CHECK-LABEL: @neg_lv_addr
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; CHECK-LABEL: loop:
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; CHECK: store i32 0, i32* %p
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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%p = getelementptr i32, i32* %loc, i32 %iv
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store i32 0, i32* %p
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_mod(i32* %loc) {
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; CHECK-LABEL: @neg_mod
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; CHECK-LABEL: exit:
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; CHECK: store i32 %iv.lcssa, i32* %loc
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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store i32 %iv, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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; Hoisting the store is actually valid here, as it dominates the load.
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define void @neg_ref(i32* %loc) {
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; CHECK-LABEL: @neg_ref
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; CHECK-LABEL: exit1:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit2:
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; CHECK: store i32 0, i32* %loc
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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store i32 0, i32* %loc
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%v = load i32, i32* %loc
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%earlycnd = icmp eq i32 %v, 198
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br i1 %earlycnd, label %exit1, label %backedge
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backedge:
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit2
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exit1:
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ret void
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exit2:
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ret void
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}
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; Hoisting the store here leads to a miscompile.
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define void @neg_ref2(i32* %loc) {
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; CHECK-LABEL: @neg_ref2
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; CHECK-LABEL: exit1:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit2:
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; CHECK: store i32 0, i32* %loc
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entry:
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store i32 198, i32* %loc
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%v = load i32, i32* %loc
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store i32 0, i32* %loc
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%earlycnd = icmp eq i32 %v, 198
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br i1 %earlycnd, label %exit1, label %backedge
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backedge:
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit2
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exit1:
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ret void
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exit2:
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ret void
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}
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declare void @modref()
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define void @neg_modref(i32* %loc) {
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; CHECK-LABEL: @neg_modref
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; CHECK-LABEL: loop:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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call void @modref()
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_fence(i32* %loc) {
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; CHECK-LABEL: @neg_fence
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; CHECK-LABEL: loop:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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fence seq_cst
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_volatile(i32* %loc) {
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; CHECK-LABEL: @neg_volatile
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; CHECK-LABEL: loop:
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; CHECK: store volatile i32 0, i32* %loc
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store volatile i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_release(i32* %loc) {
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; CHECK-LABEL: @neg_release
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; CHECK-LABEL: loop:
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; CHECK: store atomic i32 0, i32* %loc release, align 4
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store atomic i32 0, i32* %loc release, align 4
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_seq_cst(i32* %loc) {
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; CHECK-LABEL: @neg_seq_cst
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; CHECK-LABEL: loop:
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; CHECK: store atomic i32 0, i32* %loc seq_cst, align 4
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store atomic i32 0, i32* %loc seq_cst, align 4
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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declare void @maythrow() inaccessiblememonly
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define void @neg_early_exit(i32* %loc) {
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; CHECK-LABEL: @neg_early_exit
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; CHECK-LABEL: body:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %body]
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%is_null = icmp eq i32* %loc, null
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br i1 %is_null, label %exit, label %body
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body:
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call void @maythrow()
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store i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @neg_early_throw(i32* %loc) {
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; CHECK-LABEL: @neg_early_throw
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; CHECK-LABEL: loop:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: exit:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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call void @maythrow()
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store i32 0, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_late_throw(i32* %loc) {
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; CHECK-LABEL: @test_late_throw
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; CHECK-LABEL: entry:
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; CHECK: store i32 0, i32* %loc
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; CHECK-LABEL: loop:
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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call void @maythrow()
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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; TODO: could validly hoist the store here since we know what value
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; the load must observe.
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define i32 @test_dominated_read(i32* %loc) {
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; CHECK-LABEL: @test_dominated_read
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; MSSA-LABEL: entry:
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; MSSA: store i32 0, i32* %loc
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; MSSA-LABEL: loop:
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; AST-LABEL: exit:
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; AST: store i32 0, i32* %loc
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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store i32 0, i32* %loc
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%reload = load i32, i32* %loc
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%iv.next = add i32 %iv, 1
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%cmp = icmp slt i32 %iv, 200
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 %reload
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}
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; TODO: could validly hoist the store since we already hoisted the load and
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; it's no longer in the loop.
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|
|
define i32 @test_dominating_read(i32* %loc) {
|
||
|
|
; CHECK-LABEL: @test_dominating_read
|
||
|
|
; CHECK-LABEL: exit:
|
||
|
|
; CHECK: store i32 0, i32* %loc
|
||
|
|
entry:
|
||
|
|
br label %loop
|
||
|
|
|
||
|
|
loop:
|
||
|
|
%iv = phi i32 [0, %entry], [%iv.next, %loop]
|
||
|
|
%reload = load i32, i32* %loc
|
||
|
|
store i32 0, i32* %loc
|
||
|
|
%iv.next = add i32 %iv, 1
|
||
|
|
%cmp = icmp slt i32 %iv, 200
|
||
|
|
br i1 %cmp, label %loop, label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i32 %reload
|
||
|
|
}
|
||
|
|
|
||
|
|
declare void @readonly() readonly
|
||
|
|
|
||
|
|
; TODO: can legally hoist since value read by call is known
|
||
|
|
define void @test_dominated_readonly(i32* %loc) {
|
||
|
|
; CHECK-LABEL: @test_dominated_readonly
|
||
|
|
; CHECK-LABEL: loop:
|
||
|
|
; CHECK: store i32 0, i32* %loc
|
||
|
|
; CHECK-LABEL: exit:
|
||
|
|
entry:
|
||
|
|
br label %loop
|
||
|
|
|
||
|
|
loop:
|
||
|
|
%iv = phi i32 [0, %entry], [%iv.next, %loop]
|
||
|
|
store i32 0, i32* %loc
|
||
|
|
call void @readonly()
|
||
|
|
%iv.next = add i32 %iv, 1
|
||
|
|
%cmp = icmp slt i32 %iv, 200
|
||
|
|
br i1 %cmp, label %loop, label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
; While technically possible to hoist the store to %loc, this runs across
|
||
|
|
; a funemental limitation of alias sets since both stores and the call are
|
||
|
|
; within the same alias set and we can't distinguish them cheaply.
|
||
|
|
define void @test_aliasset_fn(i32* %loc, i32* %loc2) {
|
||
|
|
; CHECK-LABEL: @test_aliasset_fn
|
||
|
|
; CHECK-LABEL: loop:
|
||
|
|
; CHECK: store i32 0, i32* %loc
|
||
|
|
; CHECK-LABEL: exit:
|
||
|
|
entry:
|
||
|
|
br label %loop
|
||
|
|
|
||
|
|
loop:
|
||
|
|
%iv = phi i32 [0, %entry], [%iv.next, %loop]
|
||
|
|
store i32 0, i32* %loc
|
||
|
|
call void @readonly()
|
||
|
|
store i32 %iv, i32* %loc2
|
||
|
|
%iv.next = add i32 %iv, 1
|
||
|
|
%cmp = icmp slt i32 %iv, 200
|
||
|
|
br i1 %cmp, label %loop, label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
; If we can't tell if the value is read before the write, we can't hoist the
|
||
|
|
; write over the potential read (since we don't know the value read)
|
||
|
|
define void @neg_may_read(i32* %loc, i1 %maybe) {
|
||
|
|
; CHECK-LABEL: @neg_may_read
|
||
|
|
; CHECK-LABEL: loop:
|
||
|
|
; CHECK: store i32 0, i32* %loc
|
||
|
|
; CHECK-LABEL: exit:
|
||
|
|
entry:
|
||
|
|
br label %loop
|
||
|
|
|
||
|
|
loop:
|
||
|
|
%iv = phi i32 [0, %entry], [%iv.next, %merge]
|
||
|
|
;; maybe is a placeholder for an unanalyzable condition
|
||
|
|
br i1 %maybe, label %taken, label %merge
|
||
|
|
taken:
|
||
|
|
call void @readonly()
|
||
|
|
br label %merge
|
||
|
|
merge:
|
||
|
|
store i32 0, i32* %loc
|
||
|
|
%iv.next = add i32 %iv, 1
|
||
|
|
%cmp = icmp slt i32 %iv, 200
|
||
|
|
br i1 %cmp, label %loop, label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|