50 lines
1.3 KiB
LLVM
50 lines
1.3 KiB
LLVM
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; REQUIRES: amdgpu-registered-target && x86-registered-target
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; RUN: opt < %s -mtriple=amdgcn -jump-threading -S | FileCheck %s -check-prefixes=CHECK,DIVERGENT
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; RUN: opt < %s -mtriple=amdgcn -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,DIVERGENT
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; RUN: opt < %s -mtriple=x86_64 -jump-threading -S | FileCheck %s -check-prefixes=CHECK,UNIFORM
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; RUN: opt < %s -mtriple=x86_64 -passes=jump-threading -S | FileCheck %s -check-prefixes=CHECK,UNIFORM
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; Here we assure that for the target with no branch divergence usual Jump Threading optimization performed
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; For target with branch divergence - no optimization, so the IR is unchanged.
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declare i32 @f1()
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declare i32 @f2()
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declare void @f3()
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define i32 @test(i1 %cond) {
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; CHECK: test
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br i1 %cond, label %T1, label %F1
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; DIVERGENT: T1
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; UNIFORM-NOT: T1
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T1:
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%v1 = call i32 @f1()
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br label %Merge
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; DIVERGENT: F1
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; UNIFORM-NOT: F1
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F1:
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%v2 = call i32 @f2()
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br label %Merge
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; DIVERGENT: Merge
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; UNIFORM-NOT: Merge
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Merge:
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%A = phi i1 [true, %T1], [false, %F1]
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %A, label %T2, label %F2
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; DIVERGENT: T2
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T2:
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; UNIFORM: T2:
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; UNIFORM: %v1 = call i32 @f1()
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; UNIFORM: call void @f3()
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; UNIFORM: ret i32 %v1
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call void @f3()
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ret i32 %B
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; DIVERGENT: F2
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F2:
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; UNIFORM: F2:
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; UNIFORM: %v2 = call i32 @f2()
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; UNIFORM: ret i32 %v2
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ret i32 %B
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}
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