109 lines
6.8 KiB
LLVM
109 lines
6.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -instcombine -S < %s | FileCheck %s
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; --------------------------------------------------------------------
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; llvm.amdgcn.image.sample a16 is disabled on pre-gfx9
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; --------------------------------------------------------------------
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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define amdgpu_kernel void @image_sample_a16_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
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; CHECK-LABEL: @image_sample_a16_1d(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float [[S32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
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; CHECK-LABEL: @image_sample_a16_2d(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float [[S32]], float [[T32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%t32 = fpext half %t to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_3d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {
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; CHECK-LABEL: @image_sample_a16_3d(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float
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; CHECK-NEXT: [[R32:%.*]] = fpext half [[R:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float [[S32]], float [[T32]], float [[R32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%t32 = fpext half %t to float
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%r32 = fpext half %r to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s32, float %t32, float %r32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_cube(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {
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;
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; CHECK-LABEL: @image_sample_a16_cube(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float
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; CHECK-NEXT: [[FACE32:%.*]] = fpext half [[FACE:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 15, float [[S32]], float [[T32]], float [[FACE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%t32 = fpext half %t to float
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%face32 = fpext half %face to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 15, float %s32, float %t32, float %face32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_1darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {
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; CHECK-LABEL: @image_sample_a16_1darray(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 15, float [[S32]], float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%slice32 = fpext half %slice to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 15, float %s32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_2darray(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {
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; CHECK-LABEL: @image_sample_a16_2darray(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float
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; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32 15, float [[S32]], float [[T32]], float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = fpext half %s to float
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%t32 = fpext half %t to float
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%slice32 = fpext half %slice to float
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%res = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32 15, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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