217 lines
8.2 KiB
LLVM
217 lines
8.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -codegenprepare < %s | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; No bypassing should be done in apparently unsuitable cases.
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define void @Test_no_bypassing(i32 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_no_bypassing(
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; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[A_2:%.*]] = sub i64 -1, [[A_1]]
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; CHECK-NEXT: [[RES:%.*]] = srem i64 [[A_2]], [[B:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = zext i32 %a to i64
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; %a.2 is always negative so the division cannot be bypassed.
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%a.2 = sub i64 -1, %a.1
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%res = srem i64 %a.2, %b
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store i64 %res, i64* %retptr
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ret void
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}
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; No OR instruction is needed if one of the operands (divisor) is known
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; to fit into 32 bits.
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define void @Test_check_one_operand(i64 %a, i32 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_check_one_operand(
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; CHECK-NEXT: [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], -4294967296
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
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; CHECK: [[TMP4:%.*]] = trunc i64 [[B_1]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[A]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP10:%.*]]
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; CHECK: [[TMP9:%.*]] = sdiv i64 [[A]], [[B_1]]
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; CHECK-NEXT: br label [[TMP10]]
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; CHECK: [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
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; CHECK-NEXT: store i64 [[TMP11]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%b.1 = zext i32 %b to i64
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%res = sdiv i64 %a, %b.1
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store i64 %res, i64* %retptr
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ret void
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}
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; If both operands are known to fit into 32 bits, then replace the division
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; in-place without CFG modification.
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define void @Test_check_none(i64 %a, i32 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_check_none(
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; CHECK-NEXT: [[A_1:%.*]] = and i64 [[A:%.*]], 4294967295
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; CHECK-NEXT: [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A_1]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[B_1]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = udiv i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: store i64 [[TMP4]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = and i64 %a, 4294967295
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%b.1 = zext i32 %b to i64
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%res = udiv i64 %a.1, %b.1
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store i64 %res, i64* %retptr
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ret void
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}
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; In case of unsigned long division with a short dividend,
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; the long division is not needed any more.
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define void @Test_special_case(i32 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_special_case(
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; CHECK-NEXT: [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[A_1]], [[B:%.*]]
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; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP9:%.*]]
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; CHECK: [[TMP3:%.*]] = trunc i64 [[B]] to i32
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[A_1]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP4]], [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP9]]
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; CHECK: [[TMP10:%.*]] = phi i64 [ [[TMP7]], [[TMP2]] ], [ 0, [[TMP0:%.*]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP8]], [[TMP2]] ], [ [[A_1]], [[TMP0]] ]
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; CHECK-NEXT: [[RES:%.*]] = add i64 [[TMP10]], [[TMP11]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%a.1 = zext i32 %a to i64
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%div = udiv i64 %a.1, %b
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%rem = urem i64 %a.1, %b
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%res = add i64 %div, %rem
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store i64 %res, i64* %retptr
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ret void
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}
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; Do not bypass a division if one of the operands looks like a hash value.
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define void @Test_dont_bypass_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_xor(
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; CHECK-NEXT: [[C:%.*]] = xor i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[RES:%.*]] = udiv i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = xor i64 %a, %b
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%res = udiv i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_dont_bypass_phi_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_phi_xor(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[B:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[MERGE:%.*]], label [[XORPATH:%.*]]
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; CHECK: xorpath:
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; CHECK-NEXT: [[C:%.*]] = xor i64 [[A:%.*]], [[B]]
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[E:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[C]], [[XORPATH]] ]
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; CHECK-NEXT: [[RES:%.*]] = sdiv i64 [[E]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp = icmp eq i64 %b, 0
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br i1 %cmp, label %merge, label %xorpath
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xorpath:
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%c = xor i64 %a, %b
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br label %merge
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merge:
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%e = phi i64 [ undef, %entry ], [ %c, %xorpath ]
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%res = sdiv i64 %e, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_dont_bypass_mul_long_const(i64 %a, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_dont_bypass_mul_long_const(
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; CHECK-NEXT: [[C:%.*]] = mul i64 [[A:%.*]], 5229553307
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; CHECK-NEXT: [[RES:%.*]] = urem i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: store i64 [[RES]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = mul i64 %a, 5229553307 ; the constant doesn't fit 32 bits
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%res = urem i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_bypass_phi_mul_const(i64 %a, i64 %b, i64* %retptr) {
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; CHECK-LABEL: @Test_bypass_phi_mul_const(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_MUL:%.*]] = mul nsw i64 [[A:%.*]], 34806414968801
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; CHECK-NEXT: [[P:%.*]] = icmp sgt i64 [[A]], [[B:%.*]]
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; CHECK-NEXT: br i1 [[P]], label [[BRANCH:%.*]], label [[MERGE:%.*]]
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; CHECK: branch:
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[LHS:%.*]] = phi i64 [ 42, [[BRANCH]] ], [ [[A_MUL]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[LHS]], [[B]]
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], -4294967296
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
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; CHECK: [[TMP4:%.*]] = trunc i64 [[B]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[LHS]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: br label [[TMP10:%.*]]
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; CHECK: [[TMP9:%.*]] = sdiv i64 [[LHS]], [[B]]
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; CHECK-NEXT: br label [[TMP10]]
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; CHECK: [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
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; CHECK-NEXT: store i64 [[TMP11]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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entry:
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%a.mul = mul nsw i64 %a, 34806414968801
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%p = icmp sgt i64 %a, %b
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br i1 %p, label %branch, label %merge
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branch:
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br label %merge
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merge:
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%lhs = phi i64 [ 42, %branch ], [ %a.mul, %entry ]
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%res = sdiv i64 %lhs, %b
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store i64 %res, i64* %retptr
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ret void
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}
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define void @Test_bypass_mul_short_const(i64 %a, i64 %l, i64* %retptr) {
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; CHECK-LABEL: @Test_bypass_mul_short_const(
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; CHECK-NEXT: [[C:%.*]] = mul i64 [[A:%.*]], -42
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; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[C]], [[L:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP9:%.*]]
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; CHECK: [[TMP5:%.*]] = trunc i64 [[L]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[C]] to i32
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; CHECK-NEXT: [[TMP7:%.*]] = urem i32 [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: br label [[TMP11:%.*]]
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; CHECK: [[TMP10:%.*]] = urem i64 [[C]], [[L]]
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; CHECK-NEXT: br label [[TMP11]]
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; CHECK: [[TMP12:%.*]] = phi i64 [ [[TMP8]], [[TMP4]] ], [ [[TMP10]], [[TMP9]] ]
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; CHECK-NEXT: store i64 [[TMP12]], i64* [[RETPTR:%.*]]
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; CHECK-NEXT: ret void
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;
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%c = mul i64 %a, -42
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%res = urem i64 %c, %l
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store i64 %res, i64* %retptr
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ret void
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}
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