91 lines
3.7 KiB
LLVM
91 lines
3.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes
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; RUN: opt -S -argpromotion < %s | FileCheck %s
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; RUN: opt -S -passes=argpromotion < %s | FileCheck %s
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; Test that we only promote arguments when the caller/callee have compatible
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; function attrubtes.
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target triple = "x86_64-unknown-linux-gnu"
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define internal fastcc void @no_promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 {
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; CHECK-LABEL: define {{[^@]+}}@no_promote_avx2
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; CHECK-SAME: (<4 x i64>* [[ARG:%.*]], <4 x i64>* readonly [[ARG1:%.*]])
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = load <4 x i64>, <4 x i64>* [[ARG1]]
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; CHECK-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]]
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = load <4 x i64>, <4 x i64>* %arg1
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store <4 x i64> %tmp, <4 x i64>* %arg
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ret void
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}
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define void @no_promote(<4 x i64>* %arg) #1 {
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; CHECK-LABEL: define {{[^@]+}}@no_promote
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; CHECK-SAME: (<4 x i64>* [[ARG:%.*]])
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
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; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
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; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 32 [[TMP3]], i8 0, i64 32, i1 false)
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; CHECK-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* [[TMP2]], <4 x i64>* [[TMP]])
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; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
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; CHECK-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = alloca <4 x i64>, align 32
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%tmp2 = alloca <4 x i64>, align 32
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%tmp3 = bitcast <4 x i64>* %tmp to i8*
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call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
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call fastcc void @no_promote_avx2(<4 x i64>* %tmp2, <4 x i64>* %tmp)
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%tmp4 = load <4 x i64>, <4 x i64>* %tmp2, align 32
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store <4 x i64> %tmp4, <4 x i64>* %arg, align 2
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ret void
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}
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define internal fastcc void @promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 {
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; CHECK-LABEL: define {{[^@]+}}@promote_avx2
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; CHECK-SAME: (<4 x i64>* [[ARG:%.*]], <4 x i64> [[ARG1_VAL:%.*]])
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; CHECK-NEXT: bb:
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; CHECK-NEXT: store <4 x i64> [[ARG1_VAL]], <4 x i64>* [[ARG]]
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = load <4 x i64>, <4 x i64>* %arg1
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store <4 x i64> %tmp, <4 x i64>* %arg
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ret void
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}
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define void @promote(<4 x i64>* %arg) #0 {
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; CHECK-LABEL: define {{[^@]+}}@promote
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; CHECK-SAME: (<4 x i64>* [[ARG:%.*]])
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
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; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
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; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 32 [[TMP3]], i8 0, i64 32, i1 false)
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; CHECK-NEXT: [[TMP_VAL:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]]
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; CHECK-NEXT: call fastcc void @promote_avx2(<4 x i64>* [[TMP2]], <4 x i64> [[TMP_VAL]])
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; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
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; CHECK-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = alloca <4 x i64>, align 32
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%tmp2 = alloca <4 x i64>, align 32
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%tmp3 = bitcast <4 x i64>* %tmp to i8*
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call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
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call fastcc void @promote_avx2(<4 x i64>* %tmp2, <4 x i64>* %tmp)
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%tmp4 = load <4 x i64>, <4 x i64>* %tmp2, align 32
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store <4 x i64> %tmp4, <4 x i64>* %arg, align 2
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) #2
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attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" }
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attributes #1 = { nounwind uwtable }
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attributes #2 = { argmemonly nounwind }
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