131 lines
4.1 KiB
TableGen
131 lines
4.1 KiB
TableGen
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// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
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// Checks that tablegen correctly and completely infers subregister relations.
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include "llvm/Target/Target.td"
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class MyReg<string n, list<Register> subregs = []>
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: Register<n> {
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let Namespace = "Test";
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let SubRegs = subregs;
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let CoveredBySubRegs = 1;
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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// Register Example:
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// D0_D1 -- D0 (sub0) -- S0 (ssub0)
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// \ \- S1 (ssub1)
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// \ D1 (sub1) -- S2 (ssub2)
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// \- S3 (ssub3)
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def sub0 : SubRegIndex<32>;
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def sub1 : SubRegIndex<32, 32>;
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def sub2 : SubRegIndex<32, 64>;
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def ssub0 : SubRegIndex<16>;
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def ssub1 : SubRegIndex<16, 16>;
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def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
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def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
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def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
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def S0 : MyReg<"s0">;
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def S1 : MyReg<"s1">;
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def S2 : MyReg<"s2">;
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def S3 : MyReg<"s3">;
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def S4 : MyReg<"s4">;
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def S5 : MyReg<"s5">;
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def S6 : MyReg<"s6">;
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def S7 : MyReg<"s7">;
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def S8 : MyReg<"s8">;
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def S9 : MyReg<"s9">;
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def S10 : MyReg<"s10">;
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def S11 : MyReg<"s11">;
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def S12 : MyReg<"s12">;
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def S13 : MyReg<"s13">;
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def S14 : MyReg<"s14">;
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def S15 : MyReg<"s15">;
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def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
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let SubRegIndices = [ssub0, ssub1] in {
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def D0 : MyReg<"d0", [S0, S1]>;
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def D1 : MyReg<"d1", [S2, S3]>;
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def D2 : MyReg<"d2", [S4, S5]>;
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def D3 : MyReg<"d3", [S6, S7]>;
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def D4 : MyReg<"d4", [S8, S9]>;
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def D5 : MyReg<"d5", [S10, S11]>;
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def D6 : MyReg<"d6", [S12, S13]>;
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def D7 : MyReg<"d7", [S14, S15]>;
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}
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def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>;
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def Dtup2regs : RegisterTuples<[sub0, sub1],
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[(shl DRegs, 0), (shl DRegs, 1)]>;
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def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>;
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def Stup2_odds_regs : RegisterTuples<[ssub0, ssub1],
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[(decimate (shl SRegs, 1), 2),
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(decimate (shl SRegs, 2), 2)]>;
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def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>;
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def Stup5 : RegisterTuples<[ssub0, ssub1, ssub2, ssub3, ssub4], [
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(shl SRegs, 0),
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(shl SRegs, 1),
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(shl SRegs, 2),
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(shl SRegs, 3),
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(shl SRegs, 4)
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]>;
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def TestTarget : Target;
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// CHECK-LABEL: RegisterClass SRegs:
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// CHECK: CoveredBySubRegs: 1
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// CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
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// CHECK-LABEL: RegisterClass Stup2:
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// CHECK: CoveredBySubRegs: 1
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// CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
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// CHECK-LABEL: RegisterClass DRegs:
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// CHECK-LABEL: SubRegIndex sub0:
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// CHECK-LABEL: SubRegIndex sub1:
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// CHECK-LABEL: SubRegIndex sub2:
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// Check inferred indexes:
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// CHECK: SubRegIndex ssub1_ssub2:
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// CHECK: SubRegIndex ssub3_ssub4:
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// CHECK: SubRegIndex ssub0_ssub1_ssub2_ssub3:
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// CHECK: SubRegIndex ssub1_ssub2_ssub3_ssub4:
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// Check that all subregs are generated on some examples
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// CHECK-LABEL: Register D0:
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK-NEXT: SubReg ssub0 = S0
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// CHECK-NEXT: SubReg ssub1 = S1
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// CHECK-LABEL: Register S9_S10_S11_S12_S13:
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK-NEXT: SubReg ssub0 = S9
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// CHECK-NEXT: SubReg ssub1 = S10
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// CHECK-NEXT: SubReg ssub2 = S11
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// CHECK-NEXT: SubReg ssub3 = S12
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// CHECK-NEXT: SubReg ssub4 = S13
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// CHECK-NEXT: SubReg sub0 = S9_S10
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// CHECK-NEXT: SubReg sub1 = S11_S12
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// CHECK-NEXT: SubReg ssub1_ssub2 = D5
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// CHECK-NEXT: SubReg ssub3_ssub4 = D6
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// CHECK-NEXT: SubReg ssub1_ssub2_ssub3_ssub4 = D5_D6
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// CHECK-LABEL: Register S10_S11_S12_S13_S14:
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK-NEXT: SubReg ssub0 = S10
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// CHECK-NEXT: SubReg ssub1 = S11
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// CHECK-NEXT: SubReg ssub2 = S12
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// CHECK-NEXT: SubReg ssub3 = S13
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// CHECK-NEXT: SubReg ssub4 = S14
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// CHECK-NEXT: SubReg sub0 = D5
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// CHECK-NEXT: SubReg sub1 = D6
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// CHECK-NEXT: SubReg ssub1_ssub2 = S11_S12
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// CHECK-NEXT: SubReg ssub3_ssub4 = S13_S14
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// CHECK-NEXT: SubReg ssub0_ssub1_ssub2_ssub3 = D5_D6
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