40 lines
1.9 KiB
ArmAsm
40 lines
1.9 KiB
ArmAsm
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \
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# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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#
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# RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \
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# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
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# CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn
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# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.l.s a0, ft0, dyn
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# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn
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# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.lu.s a1, ft1, dyn
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# CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn
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# CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.s.l ft2, a2, dyn
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# CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn
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# CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.s.lu ft3, a3, dyn
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# Rounding modes
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# CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.l.s a4, ft4, rne
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# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.lu.s a5, ft5, rtz
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# CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.s.l ft6, a6, rdn
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# CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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fcvt.s.lu ft7, a7, rup
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