67 lines
2.2 KiB
Plaintext
67 lines
2.2 KiB
Plaintext
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# RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t
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# RUN: FileCheck %s < %t
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# RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t
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# RUN: FileCheck %s < %t
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# Instructions notionally in the add/sub (extended register) sheet, but with
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# invalid shift amount or "opt" field.
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[0x00 0x10 0xa0 0x0b]
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[0x00 0x10 0x60 0x0b]
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[0x00 0x14 0x20 0x0b]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Instructions notionally in the add/sub (immediate) sheet, but with
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# invalid "shift" field.
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[0xdf 0x3 0x80 0x91]
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[0xed 0x8e 0xc4 0x31]
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[0x62 0xfc 0xbf 0x11]
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[0x3 0xff 0xff 0x91]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Instructions notionally in the load/store (unsigned immediate) sheet.
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# Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11
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[0xd7 0xfc 0xff 0xb9]
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[0xd7 0xfc 0xcf 0xf9]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Instructions notionally in the floating-point <-> fixed-point conversion
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# Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register.
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[0x23 0x01 0x18 0x1e]
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[0x23 0x25 0x42 0x1e]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Instructions notionally in the logical (shifted register) sheet, but with out
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# of range shift: w-registers can only have 0-31.
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[0x00 0x80 0x00 0x0a]
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# CHECK: invalid instruction encoding
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# Instructions notionally in the move wide (immediate) sheet, but with out
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# of range shift: w-registers can only have 0 or 16.
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[0x00 0x00 0xc0 0x12]
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[0x12 0x34 0xe0 0x52]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Data-processing instructions are undefined when S=1 and for the 0b0000111
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# value in opcode:sf
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[0x00 0x00 0xc0 0x5f]
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[0x56 0x0c 0xc0 0x5a]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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# Data-processing instructions (2 source) are undefined for a value of
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# 0001xx:0:x or 0011xx:0:x for opcode:S:sf
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[0x00 0x30 0xc1 0x1a]
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[0x00 0x10 0xc1 0x1a]
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# CHECK: invalid instruction encoding
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# CHECK: invalid instruction encoding
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