107 lines
4.1 KiB
ArmAsm
107 lines
4.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7 %s
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// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V8 %s
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// Tests to check handling of sp and pc in thumb mov instructions. We
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// have to be careful about the order of things, as stdout/stderr
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// buffering means the errors appear before the non-error output, so
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// we have to put all the error checks at the top.
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// First check instructions that are never valid. These are thumb2
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// instructions that uses pc
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// t2MOVr selected because no thumb1 movs that can access high regs
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movs pc, r0
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movs r0, pc
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movs pc, pc
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// CHECK: error: operand must be a register in range [r0, r14]
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// CHECK-NEXT: movs pc, r0
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// CHECK: note: operand must be a register in range [r0, r14]
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// CHECK-NEXT: movs r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: movs r0, pc
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// CHECK: error: invalid instruction
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// CHECK-NEXT: movs pc, pc
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// mov.w selects t2MOVr
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mov.w pc, r0
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mov.w r0, pc
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mov.w pc, pc
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// CHECK: error: operand must be a register in range [r0, r14]
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// CHECK-NEXT: mov.w pc, r0
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// CHECK: note: operand must be a register in range [r0, r14]
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// CHECK-NEXT: mov.w r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: mov.w r0, pc
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// CHECK: error: invalid instruction
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// CHECK-NEXT: mov.w pc, pc
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// movs.w selects t2MOVr
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movs.w pc, r0
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movs.w r0, pc
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movs.w pc, pc
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// CHECK: error: operand must be a register in range [r0, r14]
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// CHECK-NEXT: movs.w pc, r0
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// CHECK: note: operand must be a register in range [r0, r14]
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// CHECK-NEXT: movs.w r0, pc
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// CHECK: note: invalid operand for instruction
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// CHECK-NEXT: movs.w r0, pc
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// CHECK: error: invalid instruction
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// CHECK-NEXT: movs.w pc, pc
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// Now check instructions that are invalid before ARMv8 due to SP usage
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movs sp, r0
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movs r0, sp
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movs sp, sp
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// CHECK-V7: error: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs sp, r0
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// CHECK-V7: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs r0, sp
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// CHECK-V7: error: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs sp, sp
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// CHECK-V8: movs.w sp, r0 @ encoding: [0x5f,0xea,0x00,0x0d]
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// CHECK-V8: movs.w r0, sp @ encoding: [0x5f,0xea,0x0d,0x00]
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// CHECK-V8: movs.w sp, sp @ encoding: [0x5f,0xea,0x0d,0x0d]
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mov.w sp, sp
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// CHECK-V7: error: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: mov.w sp, sp
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// CHECK-V8: mov.w sp, sp @ encoding: [0x4f,0xea,0x0d,0x0d]
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movs.w sp, r0
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movs.w r0, sp
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movs.w sp, sp
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// CHECK-V7: error: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs.w sp, r0
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// CHECK-V7: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs.w r0, sp
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// CHECK-V7: error: instruction variant requires ARMv8 or later
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// CHECK-V7-NEXT: movs.w sp, sp
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// CHECK-V8: movs.w sp, r0 @ encoding: [0x5f,0xea,0x00,0x0d]
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// CHECK-V8: movs.w r0, sp @ encoding: [0x5f,0xea,0x0d,0x00]
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// CHECK-V8: movs.w sp, sp @ encoding: [0x5f,0xea,0x0d,0x0d]
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// Now instructions that are always valid
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// mov selects tMOVr, where sp and pc are allowed
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mov sp, r0
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mov r0, sp
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mov sp, sp
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mov pc, r0
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mov r0, pc
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mov pc, pc
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// CHECK: mov sp, r0 @ encoding: [0x85,0x46]
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// CHECK: mov r0, sp @ encoding: [0x68,0x46]
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// CHECK: mov sp, sp @ encoding: [0xed,0x46]
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// CHECK: mov pc, r0 @ encoding: [0x87,0x46]
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// CHECK: mov r0, pc @ encoding: [0x78,0x46]
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// CHECK: mov pc, pc @ encoding: [0xff,0x46]
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// sp allowed in non-flags-setting t2MOVr
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mov.w sp, r0
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mov.w r0, sp
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// CHECK: mov.w sp, r0 @ encoding: [0x4f,0xea,0x00,0x0d]
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// CHECK: mov.w r0, sp @ encoding: [0x4f,0xea,0x0d,0x00]
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