71 lines
2.8 KiB
ArmAsm
71 lines
2.8 KiB
ArmAsm
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// RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
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.text
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.thumb
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// Check that the correct encoding of the add and sub instructions is
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// selected, for all combinations of flag-setting, condition and 2- or
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// 3-operand syntax.
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.arch armv6-m
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add r0, r0, r1 // T2
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add r0, r1 // T2
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adds r0, r0, r1 // T1
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adds r0, r1 // T1
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// CHECK: add r0, r1 @ encoding: [0x08,0x44]
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// CHECK: add r0, r1 @ encoding: [0x08,0x44]
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// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
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// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
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.arch armv7-m
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add r0, r0, r1 // T2, T3
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add r0, r1 // T2, T3
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adds r0, r0, r1 // T1, T3
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adds r0, r1 // T1, T3
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// CHECK: add r0, r1 @ encoding: [0x08,0x44]
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// CHECK: add r0, r1 @ encoding: [0x08,0x44]
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// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
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// CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
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itttt eq
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// CHECK: itttt eq @ encoding: [0x01,0xbf]
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addeq r0, r0, r1 // T1, T2, T3
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addeq r0, r1 // T2, T1, T3
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addseq r0, r0, r1 // T3
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addseq r0, r1 // T3
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// NOTE: Both T1 and T2 are valid for these two instructions, which one is
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// the preferred varies depending on whether the 2- or 3-operand syntax was
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// used.
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// CHECK: addeq r0, r0, r1 @ encoding: [0x40,0x18]
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// CHECK: addeq r0, r1 @ encoding: [0x08,0x44]
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// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]
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// CHECK: addseq.w r0, r0, r1 @ encoding: [0x10,0xeb,0x01,0x00]
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.arch armv6-m
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// NOTE: There is no non-flag-setting sub instruction for v6-M
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subs r0, r0, r1 // T1, T2
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subs r0, r1 // T1, T2
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// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
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// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
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.arch armv7-m
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sub r0, r0, r1 // T2
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sub r0, r1 // T2
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subs r0, r0, r1 // T1, T2
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subs r0, r1 // T1, T2
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// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]
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// CHECK: sub.w r0, r0, r1 @ encoding: [0xa0,0xeb,0x01,0x00]
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// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
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// CHECK: subs r0, r0, r1 @ encoding: [0x40,0x1a]
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itttt eq
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// CHECK: itttt eq @ encoding: [0x01,0xbf]
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subeq r0, r0, r1 // T1, T2
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subeq r0, r1 // T1, T2
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subseq r0, r0, r1 // T2
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subseq r0, r1 // T2
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// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]
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// CHECK: subeq r0, r0, r1 @ encoding: [0x40,0x1a]
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// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]
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// CHECK: subseq.w r0, r0, r1 @ encoding: [0xb0,0xeb,0x01,0x00]
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