210 lines
8.7 KiB
ArmAsm
210 lines
8.7 KiB
ArmAsm
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@ RUN: not llvm-mc < %s -triple thumbv8-unknown-unknown -show-encoding -mattr=-fp64,-fpregs64,-neon 2> %t > %t2
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@ RUN: FileCheck %s < %t --check-prefix=CHECK-ERRORS
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@ RUN: FileCheck %s < %t2
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vadd.f64 d0, d1, d2
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vsub.f64 d2, d3, d4
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vdiv.f64 d4, d5, d6
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vmul.f64 d6, d7, d8
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vnmul.f64 d8, d9, d10
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vadd.f64 d0, d1, d2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
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vmla.f64 d11, d10, d9
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vmls.f64 d8, d7, d6
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vnmla.f64 d5, d4, d3
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vnmls.f64 d2, d1, d0
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vfma.f64 d1, d2, d3
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vfms.f64 d4, d5, d6
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vfnma.f64 d7, d8, d9
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vfnms.f64 d10, d11, d12
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vmla.f64 d11, d10, d9
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vnmls.f64 d2, d1, d0
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vfma.f64 d1, d2, d3
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vfnma.f64 d7, d8, d9
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vfnms.f64 d10, d11, d12
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vneg.f64 d15, d14
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vsqrt.f64 d13, d12
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vsqrt d13, d14
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vneg.f64 d15, d14
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vsqrt.f64 d13, d12
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vsqrt d13, d14
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vcmpe.f64 d0, d1
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vcmp.f64 d2, d3
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vabs.f64 d4, d5
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vcmpe.f64 d5, #0
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vcmp.f64 d6, #0
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcmpe.f64 d0, d1
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcmp.f64 d2, d3
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcmpe.f64 d5, #0
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
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@ FIXME: overlapping aliases and a probable TableGen indeterminacy mean
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@ that the actual reason can vary by platform.
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vmov.f64 d11, d10
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@ CHECK-ERRORS: instruction requires: 64-bit fp registers
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@ CHECK-ERRORS-NEXT: vmov.f64 d11, d10
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vcvt.f64.s32 d9, s8
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vcvt.f64.u32 d7, s6
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vcvt.s32.f64 s5, d4
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vcvt.u32.f64 s3, d2
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vcvtr.s32.f64 s1, d0
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vcvtr.u32.f64 s1, d2
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vcvt.s16.f64 d3, d4, #1
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vcvt.u16.f64 d5, d6, #2
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vcvt.s32.f64 d7, d8, #3
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vcvt.u32.f64 d9, d10, #4
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vcvt.f64.s16 d11, d12, #3
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vcvt.f64.u16 d13, d14, #2
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vcvt.f64.s32 d15, d14, #1
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vcvt.f64.u32 d13, d12, #1
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.s32 d9, s8
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.u32 d7, s6
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.s32.f64 s5, d4
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.u32.f64 s3, d2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtr.s32.f64 s1, d0
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtr.u32.f64 s1, d2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.s16.f64 d3, d4, #1
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.u16.f64 d5, d6, #2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.s32.f64 d7, d8, #3
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.u32.f64 d9, d10, #4
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.s16 d11, d12, #3
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.u16 d13, d14, #2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.s32 d15, d14, #1
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvt.f64.u32 d13, d12, #1
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@ v8 operations, also double precision so make sure they're rejected.
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vselgt.f64 d0, d1, d2
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vselge.f64 d3, d4, d5
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vseleq.f64 d6, d7, d8
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vselvs.f64 d9, d10, d11
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vselgt.f64 d0, d1, d2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vselge.f64 d3, d4, d5
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vseleq.f64 d6, d7, d8
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vselvs.f64 d9, d10, d11
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vmaxnm.f64 d12, d13, d14
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vmaxnm.f64 d12, d13, d14
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vcvtb.f64.f16 d7, s8
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vcvtb.f16.f64 s9, d10
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vcvtt.f64.f16 d11, s12
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vcvtt.f16.f64 s13, d14
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtb.f64.f16 d7, s8
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtb.f16.f64 s9, d10
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtt.f64.f16 d11, s12
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vcvtt.f16.f64 s13, d14
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vrintz.f64 d15, d14
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vrintr.f64.f64 d13, d12
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vrintx.f64 d11, d10
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vrinta.f64.f64 d9, d8
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vrintn.f64 d7, d6
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vrintp.f64.f64 d5, d4
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vrintm.f64 d3, d2
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintz.f64 d15, d14
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintr.f64.f64 d13, d12
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintx.f64 d11, d10
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrinta.f64.f64 d9, d8
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintn.f64 d7, d6
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintp.f64.f64 d5, d4
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@ CHECK-ERRORS: error: instruction requires: double precision VFP
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@ CHECK-ERRORS-NEXT: vrintm.f64 d3, d2
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vstm r4, {}
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vstm r4, {d15-d30}
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vstm r4, {d15-d31}
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vstm r4, {s15-s31}
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vldm r4, {d15-d30}
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vldm r4, {d15-d31}
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vldm r4, {s15-s31}
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@ CHECK-ERRORS: error: register expected
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@ CHECK: vstmia r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
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@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
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@ CHECK: vstmia r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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@ CHECK: vldmia r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
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@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
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@ CHECK: vldmia r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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@ Double precisionish operations that actually *are* allowed.
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vldr d0, [sp]
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vstr d3, [sp]
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vldm r0, {d0, d1}
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vstm r4, {d3, d4}
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vpush {d6, d7}
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vpop {d8, d9}
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vmov r1, r0, d1
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vmov d2, r3, r4
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vmov.f64 r5, r6, d7
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vmov.f64 d8, r9, r10
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@ CHECK: vldr d0, [sp]
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@ CHECK: vstr d3, [sp]
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@ CHECK: vldmia r0, {d0, d1}
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@ CHECK: vstmia r4, {d3, d4}
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@ CHECK: vpush {d6, d7}
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@ CHECK: vpop {d8, d9}
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@ CHECK: vmov r1, r0, d1
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@ CHECK: vmov d2, r3, r4
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@ CHECK: vmov r5, r6, d7
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@ CHECK: vmov d8, r9, r10
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