52 lines
2.0 KiB
ArmAsm
52 lines
2.0 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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tbl z0.b, { z1.b, z2.b }, z3.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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tbl z0.d, { }, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: tbl z0.d, { }, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z2.b }, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { z1.d, z21.d }, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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tbl z0.d, { v0.2d, v1.2d }, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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