84 lines
3.1 KiB
ArmAsm
84 lines
3.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element widths.
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splice z0.b, p0, { z1.h, z2.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: splice z0.b, p0, { z1.h, z2.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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splice z0.b, p0, { }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: splice z0.b, p0, { }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0, { z1.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: splice z0.b, p0, { z1.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0, { z1.b, z2.b, z3.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b, z3.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0, { z1.b, z2.h }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.h }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0, { z1.b, z31.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0, { v0.4b, v1.4b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: splice z0.b, p0, { v0.4b, v1.4b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate operation
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splice z0.b, p0/z, { z1.b, z2.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: splice z0.b, p0/z, { z1.b, z2.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p0/m, { z1.b, z2.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: splice z0.b, p0/m, { z1.b, z2.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Predicate not in restricted predicate range
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splice z0.b, p8, { z1.b, z2.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31, z6
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splice z31.b, p0, { z30.b, z31.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31.b, p0/z, z6.b
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splice z31.b, p0, { z30.b, z31.b }
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b }
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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