39 lines
1.5 KiB
ArmAsm
39 lines
1.5 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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cadd z0.d, z1.d, z2.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: cadd z0.d, z1.d, z2.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid rotation
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cadd z0.d, z0.d, z1.d, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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cadd z0.d, z0.d, z1.d, #180
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #180
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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cadd z0.d, z0.d, z1.d, #450
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #450
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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cadd z0.d, z0.d, z31.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: cadd z0.d, z0.d, z31.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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