60 lines
2.2 KiB
ArmAsm
60 lines
2.2 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Invalid element kind.
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zip1 z10.h, z22.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: zip1 z10.h, z22.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Element size specifiers should match.
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zip1 z10.h, z3.h, z15.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: zip1 z10.h, z3.h, z15.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Too few operands
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zip1 z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
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// CHECK-NEXT: zip1 z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// z32 is not a valid SVE data register
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zip1 z1.s, z2.s, z32.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip1 z1.s, z2.s, z32.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// p16 is not a valid SVE predicate register
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zip1 p1.s, p2.s, p16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip1 p1.s, p2.s, p16.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining data and predicate registers as operands
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zip1 z1.s, z2.s, p3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip1 z1.s, z2.s, p3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining predicate and data registers as operands
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zip1 p1.s, p2.s, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip1 p1.s, p2.s, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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zip1 z31.d, z31.d, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: zip1 z31.d, z31.d, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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zip1 z31.d, z31.d, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: zip1 z31.d, z31.d, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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