113 lines
5.0 KiB
ArmAsm
113 lines
5.0 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-32, 28].
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ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-36, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-36, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #32, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #32, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Immediate not a multiple of four.
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ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-7, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-7, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #5, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ld4d { }, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ld4d { }, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z21.d, p5/z, z28.d
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ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21, z28
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ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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