76 lines
3.1 KiB
ArmAsm
76 lines
3.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid addressing modes.
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adr z0.s, [z0.s, z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: adr z0.s, [z0.s, z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.s, [z0.s, z0.s, lsl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
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// CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.s, [z0.s, z0.s, lsl #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
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// CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.s, [z0.s, z0.s, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
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// CHECK-NEXT: adr z0.s, [z0.s, z0.s, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.s, [z0.s, z0.s, sxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
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// CHECK-NEXT: adr z0.s, [z0.s, z0.s, sxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: adr z0.d, [z0.d, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.s, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: adr z0.d, [z0.d, z0.s, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.s, sxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: adr z0.d, [z0.d, z0.s, sxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.d, lsl #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: adr z0.d, [z0.d, z0.d, lsl #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.d, uxtw #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: adr z0.d, [z0.d, z0.d, uxtw #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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adr z0.d, [z0.d, z0.d, sxtw #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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adr z0.d, [z0.d, z0.d, sxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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adr z0.d, [z0.d, z0.d, sxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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