169 lines
7.1 KiB
ArmAsm
169 lines
7.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Register z32 does not exist.
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add z22.h, z10.h, z32.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: add z22.h, z10.h, z32.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Invalid element kind.
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add z20.h, z2.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: add z20.h, z2.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Element size specifiers should match.
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add z27.h, z11.h, z27.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: add z27.h, z11.h, z27.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Invalid predicate suffix '/a'
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add z29.d, p7/a, z29.d, z8.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'm' or 'z' predication
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// CHECK-NEXT: add z29.d, p7/a, z29.d, z8.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Missing predicate suffix
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add z29.d, p7, z29.d, z8.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: add z29.d, p7, z29.d, z8.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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add z22.b, p8/m, z22.b, z11.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: add z22.b, p8/m, z22.b, z11.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z22.h, p8/m, z22.h, z6.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: add z22.h, p8/m, z22.h, z6.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z30.s, p8/m, z30.s, z13.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: add z30.s, p8/m, z30.s, z13.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z29.d, p8/m, z29.d, z8.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: add z29.d, p8/m, z29.d, z8.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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add z19.b, p4/m, z20.b, z13.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: add z19.b, p4/m, z20.b, z13.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z9.h, p3/m, z10.h, z28.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: add z9.h, p3/m, z10.h, z28.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z5.s, p3/m, z6.s, z18.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: add z5.s, p3/m, z6.s, z18.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z9.d, p4/m, z10.d, z7.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: add z9.d, p4/m, z10.d, z7.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediates
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add z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
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// CHECK-NEXT: add z0.b, z0.b, #0, lsl #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.b, z0.b, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
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// CHECK-NEXT: add z0.b, z0.b, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.b, z0.b, #1, lsl #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
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// CHECK-NEXT: add z0.b, z0.b, #1, lsl #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.b, z0.b, #256
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
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// CHECK-NEXT: add z0.b, z0.b, #256
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.h, z0.h, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.h, z0.h, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.h, z0.h, #256, lsl #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.h, z0.h, #256, lsl #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.h, z0.h, #65536
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.h, z0.h, #65536
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.s, z0.s, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.s, z0.s, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.s, z0.s, #256, lsl #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.s, z0.s, #256, lsl #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.s, z0.s, #65536
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.s, z0.s, #65536
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.d, z0.d, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.d, z0.d, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.d, z0.d, #256, lsl #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.d, z0.d, #256, lsl #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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add z0.d, z0.d, #65536
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
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// CHECK-NEXT: add z0.d, z0.d, #65536
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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add z31.d, z31.d, #65280
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: add z31.d, z31.d, #65280
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z23.s, p0/z, z30.s
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add z23.s, z13.s, z8.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: add z23.s, z13.s, z8.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z23, z30
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add z23.s, z13.s, z8.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: add z23.s, z13.s, z8.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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