131 lines
3.8 KiB
Plaintext
131 lines
3.8 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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; ModuleID = 'sdiv.ll'
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source_filename = "sdiv.ll"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) {
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%res = sdiv i8 %arg1, %arg2
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ret i8 %res
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}
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define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) {
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%res = sdiv i16 %arg1, %arg2
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ret i16 %res
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}
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define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) {
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%res = sdiv i32 %arg1, %arg2
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ret i32 %res
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}
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...
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---
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name: test_sdiv_i8
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_sdiv_i8
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; CHECK: liveins: $edi, $esi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
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; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: [[COPY4:%[0-9]+]]:gr32_abcd = COPY [[COPY3]]
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; CHECK: [[COPY5:%[0-9]+]]:gr8_abcd_l = COPY [[COPY4]].sub_8bit
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; CHECK: $ax = MOVSX16rr8 [[COPY2]]
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; CHECK: IDIV8r [[COPY5]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
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; CHECK: [[COPY6:%[0-9]+]]:gr8 = COPY $al
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; CHECK: $al = COPY [[COPY6]]
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; CHECK: RET 0, implicit $al
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%2:gpr(s32) = COPY $edi
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%0:gpr(s8) = G_TRUNC %2(s32)
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%3:gpr(s32) = COPY $esi
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%1:gpr(s8) = G_TRUNC %3(s32)
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%4:gpr(s8) = G_SDIV %0, %1
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$al = COPY %4(s8)
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RET 0, implicit $al
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...
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---
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name: test_sdiv_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_sdiv_i16
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; CHECK: liveins: $edi, $esi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
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; CHECK: $ax = COPY [[COPY1]]
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; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax
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; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
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; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
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; CHECK: $ax = COPY [[COPY4]]
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; CHECK: RET 0, implicit $ax
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%2:gpr(s32) = COPY $edi
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%0:gpr(s16) = G_TRUNC %2(s32)
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%3:gpr(s32) = COPY $esi
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%1:gpr(s16) = G_TRUNC %3(s32)
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%4:gpr(s16) = G_SDIV %0, %1
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$ax = COPY %4(s16)
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RET 0, implicit $ax
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...
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---
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name: test_sdiv_i32
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_sdiv_i32
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; CHECK: liveins: $edi, $esi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: $eax = COPY [[COPY]]
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; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
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; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
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; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $eax
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; CHECK: $eax = COPY [[COPY2]]
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; CHECK: RET 0, implicit $eax
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%0:gpr(s32) = COPY $edi
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%1:gpr(s32) = COPY $esi
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%2:gpr(s32) = G_SDIV %0, %1
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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