132 lines
3.7 KiB
Plaintext
132 lines
3.7 KiB
Plaintext
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,SSE
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512VL,AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL
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--- |
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define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
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%ret = sub i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
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%ret = sub i32 %arg1, %arg2
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ret i32 %ret
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}
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define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = sub <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%ret = fsub <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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...
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---
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name: test_sub_i64
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr64 = COPY $rdi
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# ALL-NEXT: %1:gr64 = COPY $rsi
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# ALL-NEXT: %2:gr64 = SUB64rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_SUB %0, %1
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$rax = COPY %2(s64)
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...
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---
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name: test_sub_i32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# ALL: %0:gr32 = COPY $edi
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# ALL-NEXT: %1:gr32 = COPY $esi
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# ALL-NEXT: %2:gr32 = SUB32rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = G_SUB %0, %1
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$eax = COPY %2(s32)
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...
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---
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name: test_sub_v4i32
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# NO_AVX512VL: %0:vr128 = COPY $xmm0
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# AVX512VL: %0:vr128x = COPY $xmm0
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# NO_AVX512VL: %1:vr128 = COPY $xmm1
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# AVX512VL: %1:vr128x = COPY $xmm1
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# SSE-NEXT: %2:vr128 = PSUBDrr %0, %1
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# AVX-NEXT: %2:vr128 = VPSUBDrr %0, %1
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# AVX512F-NEXT: %2:vr128 = VPSUBDrr %0, %1
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# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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%0(<4 x s32>) = COPY $xmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<4 x s32>) = G_SUB %0, %1
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$xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit $xmm0
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...
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---
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name: test_sub_v4f32
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alignment: 16
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# NO_AVX512VL: %0:vr128 = COPY $xmm0
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# NO_AVX512VL: %1:vr128 = COPY $xmm1
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# SSE-NEXT: %2:vr128 = nofpexcept SUBPSrr %0, %1
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# AVX-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1
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# AVX512F-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1
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#
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# AVX512VL: %0:vr128x = COPY $xmm0
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# AVX512VL: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr128x = nofpexcept VSUBPSZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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%0(<4 x s32>) = COPY $xmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<4 x s32>) = G_FSUB %0, %1
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$xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit $xmm0
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...
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