62 lines
1.8 KiB
Plaintext
62 lines
1.8 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define void @test_merge_v128() {
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ret void
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}
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define void @test_merge_v256() {
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ret void
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}
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...
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---
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name: test_merge_v128
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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; ALL-LABEL: name: test_merge_v128
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; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
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; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
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; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
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; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
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; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
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; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr2]]
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; ALL: RET 0, implicit $zmm0
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%0(<4 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>)
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$zmm0 = COPY %1(<16 x s32>)
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RET 0, implicit $zmm0
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...
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---
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name: test_merge_v256
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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; ALL-LABEL: name: test_merge_v256
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; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
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; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
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; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
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; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]]
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; ALL: RET 0, implicit $zmm0
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = G_CONCAT_VECTORS %0(<8 x s32>), %0(<8 x s32>)
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$zmm0 = COPY %1(<16 x s32>)
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RET 0, implicit $zmm0
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...
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