130 lines
3.2 KiB
Plaintext
130 lines
3.2 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
|
||
|
|
# TODO: add tests for additional configuration after the legalization supported
|
||
|
|
--- |
|
||
|
|
define void @test_sub_v64i8() {
|
||
|
|
%ret = sub <64 x i8> undef, undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @test_sub_v32i16() {
|
||
|
|
%ret = sub <32 x i16> undef, undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @test_sub_v16i32() {
|
||
|
|
%ret = sub <16 x i32> undef, undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @test_sub_v8i64() {
|
||
|
|
%ret = sub <8 x i64> undef, undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_sub_v64i8
|
||
|
|
alignment: 16
|
||
|
|
legalized: false
|
||
|
|
regBankSelected: false
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
body: |
|
||
|
|
bb.1 (%ir-block.0):
|
||
|
|
liveins: $zmm0, $zmm1
|
||
|
|
|
||
|
|
; ALL-LABEL: name: test_sub_v64i8
|
||
|
|
; ALL: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
|
||
|
|
; ALL: $zmm0 = COPY [[SUB]](<64 x s8>)
|
||
|
|
; ALL: RET 0
|
||
|
|
%0(<64 x s8>) = IMPLICIT_DEF
|
||
|
|
%1(<64 x s8>) = IMPLICIT_DEF
|
||
|
|
%2(<64 x s8>) = G_SUB %0, %1
|
||
|
|
$zmm0 = COPY %2
|
||
|
|
RET 0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_sub_v32i16
|
||
|
|
alignment: 16
|
||
|
|
legalized: false
|
||
|
|
regBankSelected: false
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
body: |
|
||
|
|
bb.1 (%ir-block.0):
|
||
|
|
liveins: $zmm0, $zmm1
|
||
|
|
|
||
|
|
; ALL-LABEL: name: test_sub_v32i16
|
||
|
|
; ALL: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
|
||
|
|
; ALL: $zmm0 = COPY [[SUB]](<32 x s16>)
|
||
|
|
; ALL: RET 0
|
||
|
|
%0(<32 x s16>) = IMPLICIT_DEF
|
||
|
|
%1(<32 x s16>) = IMPLICIT_DEF
|
||
|
|
%2(<32 x s16>) = G_SUB %0, %1
|
||
|
|
$zmm0 = COPY %2
|
||
|
|
RET 0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_sub_v16i32
|
||
|
|
alignment: 16
|
||
|
|
legalized: false
|
||
|
|
regBankSelected: false
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
body: |
|
||
|
|
bb.1 (%ir-block.0):
|
||
|
|
liveins: $zmm0, $zmm1
|
||
|
|
|
||
|
|
; ALL-LABEL: name: test_sub_v16i32
|
||
|
|
; ALL: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
|
||
|
|
; ALL: $zmm0 = COPY [[SUB]](<16 x s32>)
|
||
|
|
; ALL: RET 0
|
||
|
|
%0(<16 x s32>) = IMPLICIT_DEF
|
||
|
|
%1(<16 x s32>) = IMPLICIT_DEF
|
||
|
|
%2(<16 x s32>) = G_SUB %0, %1
|
||
|
|
$zmm0 = COPY %2
|
||
|
|
RET 0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_sub_v8i64
|
||
|
|
alignment: 16
|
||
|
|
legalized: false
|
||
|
|
regBankSelected: false
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: _ }
|
||
|
|
- { id: 1, class: _ }
|
||
|
|
- { id: 2, class: _ }
|
||
|
|
body: |
|
||
|
|
bb.1 (%ir-block.0):
|
||
|
|
liveins: $zmm0, $zmm1
|
||
|
|
|
||
|
|
; ALL-LABEL: name: test_sub_v8i64
|
||
|
|
; ALL: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
; ALL: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
|
||
|
|
; ALL: $zmm0 = COPY [[SUB]](<8 x s64>)
|
||
|
|
; ALL: RET 0
|
||
|
|
%0(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
%1(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
%2(<8 x s64>) = G_SUB %0, %1
|
||
|
|
$zmm0 = COPY %2
|
||
|
|
RET 0
|
||
|
|
|
||
|
|
...
|