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llvm-for-llvmta/test/CodeGen/VE/VELIntrinsics/vmax.ll

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2022-04-25 10:02:23 +02:00
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
;;; Test vector compare and select maximum intrinsic instructions
;;;
;;; Note:
;;; We test VMAX*vvl, VMAX*vvl_v, VMAX*rvl, VMAX*rvl_v, VMAX*ivl, VMAX*ivl_v,
;;; VMAX*vvml_v, VMAX*rvml_v, VMAX*ivml_v, PVMAX*vvl, PVMAX*vvl_v, PVMAX*rvl,
;;; PVMAX*rvl_v, PVMAX*vvml_v, and PVMAX*rvml_v instructions.
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswsx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v0, %v0, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswsx_vvvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v2, %v0, %v1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvl(i32 signext %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswsx_vsvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.sx %v0, %s0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvl(i32 %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vsvl(i32, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswsx_vsvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.sx %v1, %s0, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vsvvl(i32, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvl_imm(<256 x double> %0) {
; CHECK-LABEL: vmaxswsx_vsvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v0, 8, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvl(i32 8, <256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswsx_vsvvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v1, 8, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxswsx_vvvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v2, %v0, %v1, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxswsx_vsvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.sx %v1, %s0, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswsx_vsvmvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.sx %v1, 8, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswzx_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v0, %v0, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswzx_vvvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v2, %v0, %v1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvl(i32 signext %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswzx_vsvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.zx %v0, %s0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvl(i32 %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vsvl(i32, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswzx_vsvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.zx %v1, %s0, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vsvvl(i32, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvl_imm(<256 x double> %0) {
; CHECK-LABEL: vmaxswzx_vsvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v0, 8, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvl(i32 8, <256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxswzx_vsvvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v1, 8, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxswzx_vvvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v2, %v0, %v1, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxswzx_vsvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.w.zx %v1, %s0, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxswzx_vsvmvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.w.zx %v1, 8, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxsl_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v0, %v0, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxsl_vvvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v2, %v0, %v1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvl(i64 %0, <256 x double> %1) {
; CHECK-LABEL: vmaxsl_vsvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.l %v0, %s0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvl(i64 %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vsvl(i64, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxsl_vsvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.l %v1, %s0, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vsvvl(i64, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvl_imm(<256 x double> %0) {
; CHECK-LABEL: vmaxsl_vsvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v0, 8, %v0
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvl(i64 8, <256 x double> %0, i32 256)
ret <256 x double> %2
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: vmaxsl_vsvvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v1, 8, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxsl_vvvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v2, %v0, %v1, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: vmaxsl_vsvmvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vmaxs.l %v1, %s0, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.vmaxsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @vmaxsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
; CHECK-LABEL: vmaxsl_vsvmvl_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmaxs.l %v1, 8, %v0, %vm1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vmaxsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vvvl(<256 x double> %0, <256 x double> %1) {
; CHECK-LABEL: pvmaxs_vvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvmaxs %v0, %v0, %v1
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vvvl(<256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: pvmaxs_vvvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvmaxs %v2, %v0, %v1
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vsvl(i64 %0, <256 x double> %1) {
; CHECK-LABEL: pvmaxs_vsvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvmaxs %v0, %s0, %v0
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vsvl(i64 %0, <256 x double> %1, i32 256)
ret <256 x double> %3
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vsvl(i64, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
; CHECK-LABEL: pvmaxs_vsvvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvmaxs %v1, %s0, %v0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
ret <256 x double> %4
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vsvvl(i64, <256 x double>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: pvmaxs_vvvMvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvmaxs %v2, %v0, %v1, %vm2
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
; Function Attrs: nounwind readnone
define fastcc <256 x double> @pvmaxs_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
; CHECK-LABEL: pvmaxs_vsvMvl:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 128
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvmaxs %v1, %s0, %v0, %vm2
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: b.l.t (, %s10)
%5 = tail call fast <256 x double> @llvm.ve.vl.pvmaxs.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
ret <256 x double> %5
}
; Function Attrs: nounwind readnone
declare <256 x double> @llvm.ve.vl.pvmaxs.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)