213 lines
7.9 KiB
LLVM
213 lines
7.9 KiB
LLVM
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector equivalence intrinsic instructions
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;;;
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;;; Note:
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;;; We test VEQV*vvl, VEQV*vvl_v, VEQV*rvl, VEQV*rvl_v, VEQV*vvml_v,
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;;; VEQV*rvml_v, PVEQV*vvl, PVEQV*vvl_v, PVEQV*rvl, PVEQV*rvl_v, PVEQV*vvml_v,
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;;; and PVEQV*rvml_v instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: veqv_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: veqv %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: veqv_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: veqv %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vsvl(i64 %0, <256 x double> %1) {
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; CHECK-LABEL: veqv_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: veqv %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvl(i64 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vsvl(i64, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: veqv_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: veqv %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vsvvl(i64, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: veqv_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: veqv %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @veqv_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: veqv_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: veqv %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: pveqv_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pveqv %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: pveqv_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pveqv %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vsvl(i64 %0, <256 x double> %1) {
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; CHECK-LABEL: pveqv_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pveqv %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvl(i64 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vsvl(i64, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: pveqv_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pveqv %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: pveqv_vvvMvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pveqv %v2, %v0, %v1, %vm2
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @pveqv_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: pveqv_vsvMvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pveqv %v1, %s0, %v0, %vm2
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)
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