161 lines
4.6 KiB
LLVM
161 lines
4.6 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){
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; CHECK-LABEL: cttz_2i64_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: vldr s5, .LCPI0_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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entry:
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%0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){
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; CHECK-LABEL: cttz_4i32_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #32
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: vclz.i32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 0)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_0_t(<8 x i16> %src){
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; CHECK-LABEL: cttz_8i16_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #16
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: vclz.i16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 0)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_0_t(<16 x i8> %src) {
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; CHECK-LABEL: cttz_16i8_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: vbrsr.8 q0, q0, r0
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; CHECK-NEXT: vclz.i8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){
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; CHECK-LABEL: cttz_2i64_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s6, r1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: rbit r0, r0
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; CHECK-NEXT: cset r1, ne
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; CHECK-NEXT: lsls r1, r1, #31
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: rbit r1, r1
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; CHECK-NEXT: clz r1, r1
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; CHECK-NEXT: add.w r1, r1, #32
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; CHECK-NEXT: it ne
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; CHECK-NEXT: clzne r1, r0
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; CHECK-NEXT: vmov s4, r1
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; CHECK-NEXT: vldr s5, .LCPI4_0
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; CHECK-NEXT: vmov.f32 s7, s5
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI4_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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entry:
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%0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){
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; CHECK-LABEL: cttz_4i32_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #32
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: vclz.i32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 1)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_1_t(<8 x i16> %src){
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; CHECK-LABEL: cttz_8i16_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #16
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: vclz.i16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 1)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_1_t(<16 x i8> %src) {
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; CHECK-LABEL: cttz_16i8_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: vbrsr.8 q0, q0, r0
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; CHECK-NEXT: vclz.i8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 1)
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ret <16 x i8> %0
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}
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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